56 lines
2.0 KiB
Scala
56 lines
2.0 KiB
Scala
package xiangshan
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import chisel3._
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import chisel3.stage._
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import chiseltest._
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import chiseltest.ChiselScalatestTester
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import chiseltest.VerilatorBackendAnnotation
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import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags}
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import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils}
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import org.scalatest.flatspec.AnyFlatSpec
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import org.scalatest.matchers.must.Matchers
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import firrtl.stage.RunFirrtlTransformAnnotation
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import xstransforms.PrintModuleName
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import firrtl.options.TargetDirAnnotation
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import top.ArgParser
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import xiangshan.backend.decode.DecodeUnit
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object DecodeMain extends App with HasRocketChipStageUtils {
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override def main(args: Array[String]): Unit = {
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val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args)
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// //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
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// If Complex Params are needed, wrap it with a Top Module to do dirty works,
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// and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params"
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val defaultConfig = config.alterPartial({
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// Get XSCoreParams and pass it to the "small module"
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case XSCoreParamsKey => config(XSTileKey).head.copy(
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// Example of how to change params
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IssQueSize = 12
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)
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})
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(new ChiselStage).execute(args, Seq(
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ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig)
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)))
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// // Generate files when compiling. Used by ChiselDB.
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// ElaborationArtefacts.files.foreach{ case (extension, contents) =>
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// writeOutputFile("./build", s"DecodeUnit.${extension}", contents())
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// }
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}
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}
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class DecodeUnitTest extends XSTester {
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behavior of "DecodeUnit"
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it should "pass" in {
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test(new DecodeUnit()(config)).withAnnotations(Seq(
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VerilatorBackendAnnotation,
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VerilatorFlags(Seq()),
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WriteVcdAnnotation,
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TargetDirAnnotation("./build"),
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RunFirrtlTransformAnnotation(new PrintModuleName)
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)){ dut =>
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dut.clock.step(10)
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}
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}
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} |