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171 Commits 301 Branches 5 Tags 89 MiB
Scala 94.4%
Python 4.9%
Makefile 0.4%
C 0.2%
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Zihao Yu 5a7b942b03 update sbt version 2019-03-03 16:54:26 +08:00
fpga device,VGA: rename to AXI4VGA 2019-03-01 19:57:44 +08:00
project update sbt version 2019-03-03 16:54:26 +08:00
src device,AXI4RAM: move assignments of rvalid and bvalid to AXI4Slave 2019-03-03 16:53:04 +08:00
tools/readmemh tools: add generator to generate readmemh files for loadMemoryFromFile 2019-02-21 14:02:52 +08:00
.gitignore first commit 2019-02-06 11:06:33 +08:00
Makefile Makefile: define `RANDOMIZE_REG_INIT` for emu 2019-02-25 16:29:59 +08:00
build.sbt top: add libdevice 2019-02-09 11:27:44 +08:00
scalastyle-config.xml first commit 2019-02-06 11:06:33 +08:00
scalastyle-test-config.xml first commit 2019-02-06 11:06:33 +08:00