66 lines
1.8 KiB
Tcl
66 lines
1.8 KiB
Tcl
if {[llength $argv] > 0} {
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set project_name [lindex $argv 0]
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set s [split $project_name -]
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set prj [lindex $s 0]
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set brd [lindex $s 1]
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} else {
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puts "project full name is not given!"
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return 1
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}
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proc add_bd {tcl_file} {
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source ${tcl_file}
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save_bd_design
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close_bd_design $design_name
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set_property synth_checkpoint_mode Hierarchical [get_files *${design_name}.bd]
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}
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set topmodule system_top
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set fpga_dir ${script_dir}/../..
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set project_dir ${script_dir}/build/$project_name
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set rtl_dir ${script_dir}/rtl
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set lib_dir ${fpga_dir}/lib
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set bd_dir ${script_dir}/bd
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set constr_dir ${script_dir}/constr
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set data_dir ${script_dir}/data
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set ip_dir ${script_dir}/ip
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create_project $project_name -force -dir $project_dir/ -part ${device}
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if {[info exists board]} {
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set_property board_part $board [current_project]
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}
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# lib files
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set inc_files [list \
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"[file normalize "${lib_dir}/include/axi.vh"]" \
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]
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add_files -norecurse -fileset sources_1 $inc_files
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set_property is_global_include true [get_files $inc_files]
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# Add files for noop
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lappend src_files "[file normalize "${fpga_dir}/../build/TopMain.v"]"
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add_files -norecurse -fileset sources_1 $src_files
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if {[info exists xdc_files]} {
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add_files -norecurse -fileset constrs_1 $xdc_files
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}
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# Block Designs
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add_bd ${fpga_dir}/noop.tcl
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add_bd ${bd_dir}/prm.tcl
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# setting top module for FPGA flow and simulation flow
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set_property "top" $topmodule [current_fileset]
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# setting Synthesis options
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set_property strategy {Vivado Synthesis defaults} [get_runs synth_1]
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# keep module port names in the netlist
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set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY {none} [get_runs synth_1]
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# setting Implementation options
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set_property steps.phys_opt_design.is_enabled true [get_runs impl_1]
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# update compile order
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update_compile_order -fileset sources_1
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