311 lines
13 KiB
Scala
311 lines
13 KiB
Scala
package xiangshan.cache
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import chisel3._
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import chisel3.util._
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import xiangshan._
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import xiangshan.frontend.icache._
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import utils._
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import utility._
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import chipsalliance.rocketchip.config.Parameters
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import xiangshan.backend.fu.util.HasCSRConst
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object CacheOpMap{
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def apply(opcode: String, optype: String, name: String ): Map[String, String] = {
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Map(
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"opcode" -> opcode,
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"optype" -> optype,
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"name" -> name,
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)
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}
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}
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object CacheRegMap{
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def apply(offset: String, width: String, authority: String, name: String ): Pair[String, Map[String, String]] = {
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name -> Map(
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"offset" -> offset,
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"width" -> width,
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"authority" -> authority,
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)
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}
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}
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trait CacheControlConst{
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def maxDataRowSupport = 8
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}
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abstract class CacheCtrlModule(implicit p: Parameters) extends XSModule with HasCSRConst with CacheControlConst
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object CacheInstrucion{
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def CacheOperation = List(
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CacheOpMap("b00000", "CHECK", "READ_TAG_ECC"),
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CacheOpMap("b00001", "CHECK", "READ_DATA_ECC"),
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CacheOpMap("b00010", "LOAD", "READ_TAG"),
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CacheOpMap("b00011", "LOAD", "READ_DATA"),
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CacheOpMap("b00100", "STORE", "WRITE_TAG_ECC"),
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CacheOpMap("b00101", "STORE", "WRITE_DATA_ECC"),
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CacheOpMap("b00110", "STORE", "WRITE_TAG"),
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CacheOpMap("b00111", "STORE", "WRITE_DATA"),
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CacheOpMap("b01000", "FLUSH", "FLUSH_BLOCK")
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)
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def CacheInsRegisterList = Map(
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// offset width authority name
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CacheRegMap("0", "64", "RW", "CACHE_OP"),
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CacheRegMap("1", "64", "RW", "OP_FINISH"),
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CacheRegMap("2", "64", "RW", "CACHE_LEVEL"),
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CacheRegMap("3", "64", "RW", "CACHE_WAY"),
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CacheRegMap("4", "64", "RW", "CACHE_IDX"),
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CacheRegMap("5", "64", "RW", "CACHE_BANK_NUM"),
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CacheRegMap("6", "64", "RW", "CACHE_TAG_ECC"),
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CacheRegMap("7", "64", "RW", "CACHE_TAG_BITS"), // TODO
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CacheRegMap("8", "64", "RW", "CACHE_TAG_LOW"),
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CacheRegMap("9", "64", "RW", "CACHE_TAG_HIGH"), // not used in 64 bit arch
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CacheRegMap("10", "64", "RW", "CACHE_ECC_WIDTH"), // TODO
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CacheRegMap("11", "64", "RW", "CACHE_DATA_ECC"),
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CacheRegMap("12", "64", "RW", "CACHE_DATA_0"),
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CacheRegMap("13", "64", "RW", "CACHE_DATA_1"),
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CacheRegMap("14", "64", "RW", "CACHE_DATA_2"),
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CacheRegMap("15", "64", "RW", "CACHE_DATA_3"),
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CacheRegMap("16", "64", "RW", "CACHE_DATA_4"),
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CacheRegMap("17", "64", "RW", "CACHE_DATA_5"),
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CacheRegMap("18", "64", "RW", "CACHE_DATA_6"),
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CacheRegMap("19", "64", "RW", "CACHE_DATA_7"),
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CacheRegMap("20", "64", "RW", "CACHE_ERROR"),
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)
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// Usage:
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// val cacheopMapping = CacheInstrucion.CacheInsRegisterList.map{case (name, attribute) => {
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// doSthWith(name, attribute("offset"), attribute("width"))
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// }}
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def COP_CHECK = 0.U
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def COP_LOAD = 1.U
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def COP_STORE = 2.U
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def COP_FLUSH = 3.U
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def COP_ID_ICACHE = 0
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def COP_ID_DCACHE = 1
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def COP_RESULT_CODE_IDLE = 0.U
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def COP_RESULT_CODE_OK = 1.U
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def COP_RESULT_CODE_ERROR = 2.U
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def isReadTagECC(opcode: UInt) = opcode === "b00000".U
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def isReadDataECC(opcode: UInt) = opcode === "b00001".U
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def isReadTag(opcode: UInt) = opcode === "b00010".U
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def isReadData(opcode: UInt) = opcode === "b00011".U
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def isWriteTagECC(opcode: UInt) = opcode === "b00100".U
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def isWriteDataECC(opcode: UInt) = opcode === "b00101".U
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def isWriteTag(opcode: UInt) = opcode === "b00110".U
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def isWriteData(opcode: UInt) = opcode === "b00111".U
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def isFlush(opcode: UInt) = opcode === "b01000".U
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def isReadOp(opcode: UInt) = isReadTagECC(opcode) ||
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isReadDataECC(opcode) ||
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isReadTag(opcode) ||
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isReadData(opcode)
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}
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class CacheCtrlReqInfo(implicit p: Parameters) extends XSBundle with CacheControlConst {
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val level = UInt(XLEN.W) // op target id
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val wayNum = UInt(XLEN.W)
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val index = UInt(XLEN.W)
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val opCode = UInt(XLEN.W)
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val write_tag_high = UInt(XLEN.W)
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val write_tag_low = UInt(XLEN.W)
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val write_tag_ecc = UInt(XLEN.W)
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val write_data_vec = Vec(maxDataRowSupport, UInt(XLEN.W))
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val write_data_ecc = UInt(XLEN.W)
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val bank_num = UInt(XLEN.W)
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}
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class CacheCtrlRespInfo(implicit p: Parameters) extends XSBundle with HasICacheParameters with CacheControlConst{
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val read_tag_high = UInt(XLEN.W)
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val read_tag_low = UInt(XLEN.W)
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val read_tag_ecc = UInt(XLEN.W)
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val read_data_vec = Vec(maxDataRowSupport, UInt(XLEN.W))
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val read_data_ecc = UInt(XLEN.W)
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val bank_num = UInt(XLEN.W)
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}
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class L1CacheToCsrIO(implicit p: Parameters) extends DCacheBundle {
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val distribute_csr = Flipped(new DistributedCSRIO)
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val update = new DistributedCSRUpdateReq
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}
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class L1CacheInnerOpIO(implicit p: Parameters) extends DCacheBundle {
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val req = Valid(new CacheCtrlReqInfo)
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val resp = Flipped(Valid(new CacheCtrlRespInfo))
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}
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class CSRCacheOpDecoder(decoder_name: String, id: Int)(implicit p: Parameters) extends CacheCtrlModule {
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val io = IO(new Bundle {
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val csr = new L1CacheToCsrIO
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val cache = new L1CacheInnerOpIO
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val cache_req_dup = Vec(11, Valid(new CacheCtrlReqInfo))
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val cacheOp_req_bits_opCode_dup = Output(Vec(11, UInt(XLEN.W)))
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val error = Flipped(new L1CacheErrorInfo)
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})
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// CSRCacheOpDecoder state
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val wait_csr_op_req = RegInit(true.B) // waiting for csr "CACHE_OP" being write
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val wait_cache_op_resp = RegInit(false.B) // waiting for dcache to finish dcache op
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val schedule_csr_op_resp_data = RegInit(false.B) // ready to write data readed from cache back to csr
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val schedule_csr_op_resp_finish = RegInit(false.B) // ready to write "OP_FINISH" csr
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// val cache_op_resp_timer = RegInit(0.U(4.W))
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val data_transfer_finished = WireInit(false.B)
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val data_transfer_cnt = RegInit(0.U(log2Up(maxDataRowSupport).W))
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// Translate CSR write to cache op
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val translated_cache_req = Reg(new CacheCtrlReqInfo)
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val translated_cache_req_opCode_dup = Reg(Vec(11, UInt(XLEN.W)))
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println("Cache op decoder (" + decoder_name + "):")
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println(" Id " + id)
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// CacheInsRegisterList.map{case (name, attribute) => {
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// println(" Register CSR mirror " + name)
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// }}
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def cacheop_csr_is_being_write(csr_name: String): Bool = {
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io.csr.distribute_csr.w.bits.addr === (CacheInstrucion.CacheInsRegisterList(csr_name)("offset").toInt + Scachebase).U &&
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io.csr.distribute_csr.w.valid
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}
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def update_cache_req_when_write(csr_name: String, req_field: Data) = {
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when(
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cacheop_csr_is_being_write(csr_name)
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){
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req_field := io.csr.distribute_csr.w.bits.data
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assert(wait_csr_op_req)
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}
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}
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update_cache_req_when_write("CACHE_OP", translated_cache_req.opCode)
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translated_cache_req_opCode_dup.map(dup => update_cache_req_when_write("CACHE_OP", dup))
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update_cache_req_when_write("CACHE_LEVEL", translated_cache_req.level)
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update_cache_req_when_write("CACHE_WAY", translated_cache_req.wayNum)
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update_cache_req_when_write("CACHE_IDX", translated_cache_req.index)
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update_cache_req_when_write("CACHE_BANK_NUM", translated_cache_req.bank_num)
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update_cache_req_when_write("CACHE_TAG_HIGH", translated_cache_req.write_tag_high)
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update_cache_req_when_write("CACHE_TAG_LOW", translated_cache_req.write_tag_low)
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update_cache_req_when_write("CACHE_TAG_ECC", translated_cache_req.write_tag_ecc)
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update_cache_req_when_write("CACHE_DATA_0", translated_cache_req.write_data_vec(0))
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update_cache_req_when_write("CACHE_DATA_1", translated_cache_req.write_data_vec(1))
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update_cache_req_when_write("CACHE_DATA_2", translated_cache_req.write_data_vec(2))
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update_cache_req_when_write("CACHE_DATA_3", translated_cache_req.write_data_vec(3))
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update_cache_req_when_write("CACHE_DATA_4", translated_cache_req.write_data_vec(4))
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update_cache_req_when_write("CACHE_DATA_5", translated_cache_req.write_data_vec(5))
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update_cache_req_when_write("CACHE_DATA_6", translated_cache_req.write_data_vec(6))
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update_cache_req_when_write("CACHE_DATA_7", translated_cache_req.write_data_vec(7))
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update_cache_req_when_write("CACHE_DATA_ECC", translated_cache_req.write_data_ecc)
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val cache_op_start = WireInit(cacheop_csr_is_being_write("CACHE_OP") && id.U === translated_cache_req.level)
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when(cache_op_start) {
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wait_csr_op_req := false.B
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}
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// Send cache op to cache
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io.cache.req.valid := RegNext(cache_op_start)
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io.cache_req_dup.map( dup => dup.valid := RegNext(cache_op_start) )
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io.cache.req.bits := translated_cache_req
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io.cache_req_dup.map( dup => dup.bits := translated_cache_req )
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when(io.cache.req.fire()){
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wait_cache_op_resp := true.B
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}
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io.cacheOp_req_bits_opCode_dup.zipWithIndex.map{ case (dup, i) => dup := translated_cache_req_opCode_dup(i) }
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// Receive cache op resp from cache
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val raw_cache_resp = Reg(new CacheCtrlRespInfo)
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when(io.cache.resp.fire()){
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wait_cache_op_resp := false.B
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raw_cache_resp := io.cache.resp.bits
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when(CacheInstrucion.isReadOp(translated_cache_req.opCode)){
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schedule_csr_op_resp_data := true.B
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schedule_csr_op_resp_finish := false.B
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assert(data_transfer_cnt === 0.U)
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}.otherwise{
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schedule_csr_op_resp_data := false.B
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schedule_csr_op_resp_finish := true.B
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}
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}
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// Translate cache op resp to CSR write, send it back to CSR
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when(io.csr.update.w.fire() && schedule_csr_op_resp_data && data_transfer_finished){
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schedule_csr_op_resp_data := false.B
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schedule_csr_op_resp_finish := true.B
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}
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when(io.csr.update.w.fire() && schedule_csr_op_resp_finish){
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schedule_csr_op_resp_finish := false.B
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wait_csr_op_req := true.B
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}
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io.csr.update.w.valid := schedule_csr_op_resp_data || schedule_csr_op_resp_finish
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io.csr.update.w.bits := DontCare
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val isReadTagECC = WireInit(CacheInstrucion.isReadTagECC(translated_cache_req_opCode_dup(0)))
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val isReadDataECC = WireInit(CacheInstrucion.isReadDataECC(translated_cache_req_opCode_dup(0)))
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val isReadTag = WireInit(CacheInstrucion.isReadTag(translated_cache_req.opCode))
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val isReadData = WireInit(CacheInstrucion.isReadData(translated_cache_req.opCode))
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when(schedule_csr_op_resp_data){
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io.csr.update.w.bits.addr := Mux1H(List(
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isReadTagECC -> (CacheInstrucion.CacheInsRegisterList("CACHE_TAG_ECC")("offset").toInt + Scachebase).U,
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isReadDataECC -> (CacheInstrucion.CacheInsRegisterList("CACHE_DATA_ECC")("offset").toInt + Scachebase).U,
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isReadTag -> ((CacheInstrucion.CacheInsRegisterList("CACHE_TAG_LOW")("offset").toInt + Scachebase).U + data_transfer_cnt),
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isReadData -> ((CacheInstrucion.CacheInsRegisterList("CACHE_DATA_0")("offset").toInt + Scachebase).U + data_transfer_cnt),
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))
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io.csr.update.w.bits.data := Mux1H(List(
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isReadTagECC -> raw_cache_resp.read_tag_ecc,
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isReadDataECC -> raw_cache_resp.read_data_ecc,
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isReadTag -> raw_cache_resp.read_tag_low,
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isReadData -> raw_cache_resp.read_data_vec(data_transfer_cnt),
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))
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data_transfer_finished := Mux(isReadData,
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data_transfer_cnt === (maxDataRowSupport-1).U,
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true.B
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)
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data_transfer_cnt := data_transfer_cnt + 1.U
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}
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when(schedule_csr_op_resp_finish){
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io.csr.update.w.bits.addr := (CacheInstrucion.CacheInsRegisterList("OP_FINISH")("offset").toInt + Scachebase).U
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io.csr.update.w.bits.data := CacheInstrucion.COP_RESULT_CODE_OK
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data_transfer_cnt := 0.U
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}
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val error = DelayN(io.error, 1)
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when(error.report_to_beu) {
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io.csr.update.w.bits.addr := (CacheInstrucion.CacheInsRegisterList("CACHE_ERROR")("offset").toInt + Scachebase).U
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io.csr.update.w.bits.data := error.asUInt
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io.csr.update.w.valid := true.B
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}
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}
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class CSRCacheErrorDecoder(implicit p: Parameters) extends CacheCtrlModule {
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val io = IO(new Bundle{
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val encoded_cache_error = Input(UInt())
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})
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val encoded_cache_error = io.encoded_cache_error
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def print_cache_error_flag(flag: Bool, desc: String) = {
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when(flag){
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printf(" " + desc + "\n")
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}
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}
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val decoded_cache_error = WireInit(encoded_cache_error.asTypeOf(new L1CacheErrorInfo))
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when(decoded_cache_error.valid && !RegNext(decoded_cache_error.valid)){
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printf("CACHE_ERROR CSR reported an error:\n")
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printf(" paddr 0x%x\n", decoded_cache_error.paddr)
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print_cache_error_flag(decoded_cache_error.report_to_beu, "report to bus error unit")
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print_cache_error_flag(decoded_cache_error.source.tag, "tag")
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print_cache_error_flag(decoded_cache_error.source.data, "data")
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print_cache_error_flag(decoded_cache_error.source.l2, "l2")
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print_cache_error_flag(decoded_cache_error.opType.fetch, "fetch")
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print_cache_error_flag(decoded_cache_error.opType.load, "load")
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print_cache_error_flag(decoded_cache_error.opType.store, "store")
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print_cache_error_flag(decoded_cache_error.opType.probe, "probe")
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print_cache_error_flag(decoded_cache_error.opType.release, "release")
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print_cache_error_flag(decoded_cache_error.opType.atom, "atom")
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printf("It should not happen in normal execution flow\n")
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}
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}
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