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fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#418:Scheduled
master
2025-10-08 15:33:20 +08:00
0s
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#417:Scheduled
master
2025-10-08 15:33:20 +08:00
0s
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#416:Scheduled
master
2025-10-07 15:33:20 +08:00
0s
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#415:Scheduled
master
2025-10-06 15:33:20 +08:00
0s
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#414:Scheduled
master
2025-10-05 15:33:20 +08:00
0s
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#413:Scheduled
master
2025-10-04 15:33:20 +08:00
0s
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#412:Scheduled
master
2025-10-03 15:33:20 +08:00
0s
fix(TLB): fix incorrect TLB level refill when has exception (#5087)
#411:Scheduled
master
2025-10-02 15:33:20 +08:00
0s
feat(CLINT): add new clint to match 1:1 ration between CLINT and HART (#4991)
#407:Scheduled
#5082/merge
2025-10-01 16:04:22 +08:00
0s
feat(CLINT): add new clint to match 1:1 ration between CLINT and HART (#4991)
#405:Scheduled
master
2025-09-30 16:05:28 +08:00
0s
fix(misalign): fixed a hang issue caused by vector misalign (#4914)
#399:Scheduled
master
2025-09-29 10:15:14 +08:00
0s
fix(misalign): fixed a hang issue caused by vector misalign (#4914)
#398:Scheduled
master
2025-09-29 10:04:22 +08:00
0s
feat(config): add CVM-related yaml configs (#4924)
#395:Scheduled
master
2025-08-03 00:50:10 +08:00
0s
feat(config): add CVM-related yaml configs (#4924)
#394:Scheduled
master
2025-08-02 15:33:07 +08:00
0s
fix(Bitmap): fix X-prop caused by using RRArbiter in Bitmap module (#4920)
#389:Scheduled
master
2025-07-31 18:45:25 +08:00
0s
fix(VSegmentUnit): adjust the fullva bit width of the tlb req (#4892)
#384:Scheduled
master
2025-07-30 17:54:14 +08:00
0s
fix(ICache,Ifu): set memBackTypeMM and memPageTypeNC correctly (#4898)
#381:Scheduled
new-frontend-part1
2025-07-30 16:30:55 +08:00
0s
fix(ICache,Ifu): set memBackTypeMM and memPageTypeNC correctly (#4898)
#380:Scheduled
#4910/merge
2025-07-29 16:30:10 +08:00
0s
fix(ICache,Ifu): set memBackTypeMM and memPageTypeNC correctly (#4898)
#379:Scheduled
#4910/merge
2025-07-28 16:30:18 +08:00
0s
fix(ICache,Ifu): set memBackTypeMM and memPageTypeNC correctly (#4898)
#377:Scheduled
master
2025-07-27 16:30:15 +08:00
0s
fix(Ifu,InstrUncache): flush mmio fsm (#4903)
#371:Scheduled
master
2025-07-25 15:40:14 +08:00
0s
fix(MainPipe): fix `s3_data_error_beu` generate logic avoid x state (#4899)
#368:Scheduled
master
2025-07-24 23:35:09 +08:00
0s
submodule(ready-to-run): bump nemu ref in ready-to-run (#4887)
#363:Scheduled
#4875/merge
2025-07-24 17:26:03 +08:00
0s
ci(nightly): fix nightly ci for kunminghu-v3 (#4897)
#360:Scheduled
master
2025-07-22 19:06:09 +08:00
0s
docs: add document license to README (#4895)
#355:Scheduled
master
2025-07-21 18:35:27 +08:00
0s
docs: add document license to README (#4895)
#354:Scheduled
master
2025-07-21 15:33:24 +08:00
0s
docs: add document license to README (#4895)
#353:Scheduled
master
2025-07-20 15:33:26 +08:00
0s
fix(ifu): fix speculative instruction fetch in MMIO region. (#4881)
#348:Scheduled
master
2025-07-19 01:15:28 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4884)
#343:Scheduled
master
2025-07-17 16:35:47 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4884)
#342:Scheduled
master
2025-07-17 15:33:24 +08:00
0s
fix(config): add missing IMSICParams in Poweroff (#4857)
#339:Scheduled
master
2025-07-15 15:35:31 +08:00
0s
fix(config): add missing IMSICParams in Poweroff (#4857)
#338:Scheduled
master
2025-07-15 15:33:23 +08:00
0s
fix(config): add missing IMSICParams in Poweroff (#4857)
#337:Scheduled
master
2025-07-14 15:33:24 +08:00
0s
fix(config): add missing IMSICParams in Poweroff (#4857)
#336:Scheduled
master
2025-07-13 15:33:23 +08:00
0s
fix(rab): correct ismove sent to rab for instraction page fault caused by move elimination (#4874)
#333:Scheduled
master
2025-07-11 21:45:28 +08:00
0s
fix(StoreQueue): adjust the timing of the cbozero setting status (#4867)
#328:Scheduled
master
2025-07-10 21:15:28 +08:00
0s
fix(StoreQueue): adjust the timing of the cbozero setting status (#4867)
#327:Scheduled
master
2025-07-10 15:33:23 +08:00
0s
fix(StoreQueue): fix misalign forward fail stall (#4859)
#324:Scheduled
master
2025-07-08 20:15:28 +08:00
0s
fix(VMergeBuffer): fix gpaddr calculation when Unit-Stride triggers an exception (#4865)
#317:Scheduled
master
2025-07-07 19:45:27 +08:00
0s
fix(VMergeBuffer): fix gpaddr calculation when Unit-Stride triggers an exception (#4865)
#316:Scheduled
master
2025-07-07 15:33:23 +08:00
0s
fix(MainPipe): fix mainpipe x state when miss request after miss request (#4856)
#313:Scheduled
master
2025-07-06 02:55:26 +08:00
0s
fix(MainPipe): fix mainpipe x state when miss request after miss request (#4856)
#312:Scheduled
master
2025-07-05 15:33:23 +08:00
0s
fix(VSegmentUnit): flush sbuffer until sbuffer is empty (#4853)
#309:Scheduled
master
2025-07-03 17:45:28 +08:00
0s
fix(L2Top): remove redundant `reset` for `hartIsInReset` (#4844)
#306:Scheduled
#4849/merge
2025-07-03 17:25:23 +08:00
0s
fix(L2Top): remove redundant `reset` for `hartIsInReset` (#4844)
#305:Scheduled
master
2025-07-02 17:25:23 +08:00
0s
fix(L2Top): remove redundant `reset` for `hartIsInReset` (#4844)
#303:Scheduled
master
2025-07-01 15:33:23 +08:00
0s
fix(L2Top): remove redundant `reset` for `hartIsInReset` (#4844)
#302:Scheduled
master
2025-06-30 15:33:23 +08:00
0s
fix(L2Top): remove redundant `reset` for `hartIsInReset` (#4844)
#301:Scheduled
master
2025-06-29 15:33:23 +08:00
0s
submodule(ready-to-run): bump nemu ref in ready-to-run (#4835)
#297:Scheduled
feat-v3-bpu-tmp
2025-06-28 17:25:24 +08:00
0s
submodule(ready-to-run): bump nemu ref in ready-to-run (#4835)
#296:Scheduled
feat-v3-ubtb
2025-06-27 17:25:24 +08:00
0s
submodule(ready-to-run): bump nemu ref in ready-to-run (#4835)
#295:Scheduled
master
2025-06-26 17:25:24 +08:00
0s
fix(ICache): do not check meta(1) parity if !s1_doubleline (#4814)
#292:Scheduled
master
2025-06-24 21:25:28 +08:00
0s
fix(csr): set xstatus.VS dirty when a vector memory access instr has exception (#4817)
#287:Scheduled
master
2025-06-23 20:55:28 +08:00
0s
fix(AXI4Lite): add `wstrb` to AXI4Lite interface (#4818)
#284:Scheduled
#4706/merge
2025-06-23 17:25:34 +08:00
0s
fix(AXI4Lite): add `wstrb` to AXI4Lite interface (#4818)
#283:Scheduled
#4706/merge
2025-06-22 17:25:24 +08:00
0s
fix(AXI4Lite): add `wstrb` to AXI4Lite interface (#4818)
#282:Scheduled
#4706/merge
2025-06-21 17:25:24 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4816)
#279:Scheduled
master
2025-06-19 18:56:38 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4816)
#278:Scheduled
master
2025-06-19 15:33:34 +08:00
0s
fix(csr): fix CSR rData when CSR claim IMSIC (#4802)
#275:Scheduled
kunminghu-v2r2-20250615
2025-06-18 17:26:34 +08:00
0s
fix(csr): fix CSR rData when CSR claim IMSIC (#4802)
#274:Scheduled
master
2025-06-17 17:26:34 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4808)
#271:Scheduled
#4809/merge
2025-06-16 17:26:34 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4808)
#270:Scheduled
#4809/merge
2025-06-15 17:26:34 +08:00
0s
fix(vsegment): vec segment should also respond to bus error (#4800)
#266:Scheduled
master
2025-06-13 15:56:39 +08:00
0s
fix(vsegment): vec segment should also respond to bus error (#4800)
#265:Scheduled
master
2025-06-13 15:33:34 +08:00
0s
fix(vsegment): vec segment should also respond to bus error (#4800)
#264:Scheduled
master
2025-06-12 15:33:34 +08:00
0s
fix(TLB): correct gpaddr generating for handle_block (#4793)
#259:Scheduled
master
2025-06-10 22:36:38 +08:00
0s
fix(MainPipe): fix probe/replace stall for alias scheme (#4741)
#256:Scheduled
master
2025-06-09 22:06:39 +08:00
0s
fix(MainPipe): fix probe/replace stall for alias scheme (#4741)
#255:Scheduled
master
2025-06-09 15:33:34 +08:00
0s
fix(MainPipe): fix probe/replace stall for alias scheme (#4741)
#254:Scheduled
master
2025-06-08 15:33:34 +08:00
0s
fix(MainPipe): fix probe/replace stall for alias scheme (#4741)
#253:Scheduled
master
2025-06-07 15:33:34 +08:00
0s
fix(StoreQueue): fix vecExceptionFlag when flow is misaligned (#4731)
#246:Scheduled
master
2025-06-05 18:06:39 +08:00
0s
ci: upload lowpower verilog for verification (#4771)
#241:Scheduled
master
2025-06-04 17:36:38 +08:00
0s
fix(LoadUnit): no longer allow tlb missing misaligned load to enter misalignbuffer (#4760)
#234:Scheduled
master
2025-06-03 17:06:39 +08:00
0s
fix(LoadUnit): no longer allow tlb missing misaligned load to enter misalignbuffer (#4760)
#233:Scheduled
master
2025-06-03 15:33:34 +08:00
0s
fix(LoadUnit): no longer allow tlb missing misaligned load to enter misalignbuffer (#4760)
#232:Scheduled
master
2025-06-02 15:33:34 +08:00
0s
fix(LoadPipe): load will not enter missqueue when btot grow fail (#4750)
#229:Scheduled
master
2025-05-31 23:46:38 +08:00
0s
fix(LLPTW): first_s2xlate_fault should be true when check_g_perm_fail (#4754)
#226:Scheduled
master
2025-05-30 23:16:38 +08:00
0s
fix(csr): skip CSR read xtopi (#4742)
#220:Scheduled
master
2025-05-29 22:50:20 +08:00
0s
misc: update CODEOWNERS (#4745)
#217:Scheduled
master
2025-05-28 22:20:19 +08:00
0s
refactor(XSNoCTop): Move LowPower logic to trait method buildLowPower() (#4708)
#213:Scheduled
master
2025-05-28 14:10:22 +08:00
0s
refactor(Config): refactor `DFT` option passing method (#4643)
#208:Scheduled
master
2025-05-26 21:20:19 +08:00
0s
fix(PMA): sc / amo should report af when !atomic (#4724)
#203:Scheduled
master
2025-05-25 20:50:18 +08:00
0s
fix(MainPipe): only requests from sbuffer are allowed to return replay response (#4720)
#199:Scheduled
master
2025-05-24 20:20:20 +08:00
0s
fix(MainPipe): only requests from sbuffer are allowed to return replay response (#4720)
#198:Scheduled
master
2025-05-24 15:33:15 +08:00
0s
fix: safe protection before entering of WFI (backend/ifu/mmu/lsu) (#4691)
#194:Scheduled
master
2025-05-22 19:20:21 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4710)
#189:Scheduled
master
2025-05-21 18:50:20 +08:00
0s
fix(StoreQueue): not do nc store when having exception (#4661)
#184:Scheduled
master
2025-05-20 18:20:20 +08:00
0s
submodule(ready-to-run): bump ready-to-run to add context CSRs
#179:Scheduled
fix-add-ncmm-diff
2025-05-20 17:40:15 +08:00
0s
submodule(ready-to-run): bump ready-to-run to add context CSRs
#177:Scheduled
master
2025-05-19 17:40:15 +08:00
0s
submodule(ready-to-run): bump ready-to-run to add context CSRs
#176:Scheduled
master
2025-05-18 15:33:15 +08:00
0s
submodule(ready-to-run): Bump nemu ref in ready-to-run
#171:Scheduled
master
2025-05-16 16:20:23 +08:00
0s
fix(docker): Forward variables in the make command line to docker (#4686)
#168:Scheduled
master
2025-05-16 00:00:20 +08:00
0s
fix(StoreQueue): fix timeout of vecExceptionFlag when redirect (#4660)
#165:Scheduled
master
2025-05-14 23:30:19 +08:00
0s
ci(docker): Run image build job w/o push for PR check (#4681)
#161:Scheduled
master
2025-05-14 15:20:19 +08:00
0s
fix(docker): fix docker image build by moving MILL_OUTPUT_DIR to tmpfs (#4679)
#158:Scheduled
master
2025-05-12 22:30:18 +08:00
0s
fix(docker): fix docker image build by moving MILL_OUTPUT_DIR to tmpfs (#4679)
#157:Scheduled
master
2025-05-12 15:33:15 +08:00
0s
fix(CSR): fix trapInst update logic (#4671)
#154:Scheduled
master
2025-05-10 21:30:19 +08:00
0s
fix(MMU): fix MMU hit logic for napot cases (#4659)
#150:Scheduled
master
2025-05-10 05:10:20 +08:00
0s
fix(LCOFI): fix writable of LCOFI bit(13) of mvip/mvien/hvip/hvien (#4648)
#147:Scheduled
master
2025-05-08 20:30:20 +08:00
0s
submodule(ready-to-run): bump ready-to-run to fix smstateen
#145:Scheduled
master
2025-05-07 20:00:19 +08:00
0s
submodule(ready-to-run): bump ready-to-run to fix smstateen
#144:Scheduled
master
2025-05-07 15:33:15 +08:00
0s
submodule(ready-to-run): bump ready-to-run to fix smstateen
#143:Scheduled
master
2025-05-06 15:33:15 +08:00
0s
submodule(ready-to-run): bump ready-to-run to fix smstateen
#142:Scheduled
master
2025-05-05 15:33:15 +08:00
0s
submodule(ready-to-run): bump ready-to-run to fix smstateen
#141:Scheduled
master
2025-05-04 15:33:15 +08:00
0s
submodule(ready-to-run): bump ready-to-run to fix smstateen
#140:Scheduled
master
2025-05-03 15:33:15 +08:00
0s
fix(StoreQueue): setting addrvalid on misalign revoke (#4650)
#138:Scheduled
master
2025-05-02 01:10:18 +08:00
0s
fix(LoadUnit): perfetch no longer generates nc access (#4636)
#136:Scheduled
master
2025-04-30 16:30:19 +08:00
0s
fix(StoreUnit): optimize the code by StoreUnit Code Review (#4627)
#133:Scheduled
#4635/merge
2025-04-30 17:40:15 +08:00
0s
fix(StoreUnit): optimize the code by StoreUnit Code Review (#4627)
#132:Scheduled
master
2025-04-29 16:00:21 +08:00
0s
submodule(utility): remove unused println of PerfCCT (#4633)
#128:Scheduled
master
2025-04-28 07:20:18 +08:00
0s
fix(StoreQueue): add nc_req_ack state to avoid duplicated request (#4625)
#125:Scheduled
master
2025-04-26 22:40:19 +08:00
0s
fix(csr): filter out Read-Only CSR in regOut (#4412)
#123:Scheduled
master
2025-04-25 22:10:18 +08:00
0s
fix(intr,difftest): add interrupt delegate (#4516)
#120:Scheduled
master
2025-04-24 21:40:19 +08:00
0s
submodule(ready-to-run): Bump nemu ref in ready-to-run
#116:Scheduled
master
2025-04-23 21:10:19 +08:00
0s
chore(Parameters): remove the incorrect parameter description (#4391)
#113:Scheduled
master
2025-04-22 20:40:20 +08:00
0s
fix(LLPTW): dup_wait_resp should not send last_hptw_req when excp (#4596)
#109:Scheduled
master
2025-04-21 20:10:21 +08:00
0s
fix(LoadUnit): fix ldld && stld query revoke logic (#4580)
#106:Scheduled
master
2025-04-20 19:40:18 +08:00
0s
fix(LoadUnit): fix ldld && stld query revoke logic (#4580)
#105:Scheduled
master
2025-04-20 15:33:15 +08:00
0s
submodule(ready-to-run): bump nemu ref in ready-to-run (#4566)
#103:Scheduled
master
2025-04-18 18:40:19 +08:00
0s
fix(exceptionGen): clear isEnqExcp when older or curr wb exception coming (#4570)
#101:Scheduled
master
2025-04-18 02:20:18 +08:00
0s
fix(DFT): fix `DFT` cgen connection (#4565)
#98:Scheduled
master
2025-04-16 17:40:18 +08:00
0s
fix: add low power related logic (#4554)
#95:Scheduled
master
2025-04-15 17:10:19 +08:00
0s
fix(L2TlbPrefetch): fix flush condition of L2 TLB Prefetch (#4541)
#92:Scheduled
master
2025-04-14 16:40:19 +08:00
0s
submodule(chiselAIA): bump chiselAIA to fix `imsic.toCSR.illegal` (#4546)
#89:Scheduled
master
2025-04-14 00:20:18 +08:00
0s
fix(StoreQueue): keep readPtr until slave ack when outstanding (#4531)
#87:Scheduled
master
2025-04-12 15:40:19 +08:00
0s
fix(StoreQueue): keep readPtr until slave ack when outstanding (#4531)
#86:Scheduled
master
2025-04-12 15:33:15 +08:00
0s
feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)
#84:Scheduled
master
2025-04-10 22:50:18 +08:00
0s
fix(XSNoCTop): fix wfi wakeup by snoop (#4521)
#81:Scheduled
master
2025-04-09 22:20:21 +08:00
0s
fix(Uncache): uncache mm store needs difftest to update goldenmem (#4470)
#77:Scheduled
master
2025-04-08 21:50:21 +08:00
0s
chore: add code owner of top (#4500)
#73:Scheduled
master
2025-04-07 21:20:19 +08:00
0s
ci: use fst instead of vcd (#4503)
#70:Scheduled
master
2025-04-06 20:50:17 +08:00
0s
ci: use fst instead of vcd (#4503)
#69:Scheduled
master
2025-04-06 15:33:15 +08:00
0s
feat(backend): make wfi timeout configurable (#4491)
#66:Scheduled
master
2025-04-04 19:50:18 +08:00
0s
fix(FTB, FTQ): dont use CPL2 SplittedSRAM (#4485)
#63:Scheduled
master
2025-04-04 03:30:17 +08:00
0s
fix(AXI4Memory): remove `AWLEN == 0` Check (#4383)
#59:Scheduled
#4489/merge
2025-04-03 17:40:15 +08:00
0s
ci(perf): more execution time and use summary instead of artifact (#4486)
#56:Scheduled
master
2025-04-01 18:20:20 +08:00
0s
submodule(ready-to-run): bump nemu ref in ready-to-run (#4478)
#53:Scheduled
master
2025-03-31 17:50:20 +08:00
0s
submodule(ready-to-run): bump nemu ref in ready-to-run (#4478)
#52:Scheduled
master
2025-03-31 15:33:15 +08:00
0s
submodule(CoupledL2): bump CoupledL2 (#4469)
#49:Scheduled
master
2025-03-29 16:50:18 +08:00
0s
fix(TLB): L1 TLB will not save the high bit of PPN (#4455)
#46:Scheduled
master
2025-03-28 16:20:20 +08:00
0s
fix(FusionDecoder): tie output to false when disabled (#4456)
#44:Scheduled
master
2025-03-28 00:00:21 +08:00
0s
fix(FusionDecoder): tie output to false when disabled (#4456)
#43:Scheduled
master
2025-03-27 15:33:15 +08:00
0s
fix(TLB): fix a typo about napot scenario (#4454)
#40:Scheduled
master
2025-03-25 23:00:26 +08:00
0s
fix(TLB): fix a typo about napot scenario (#4454)
#39:Scheduled
master
2025-03-25 15:33:15 +08:00
0s
fix(difftest, CSR): sync non-reg interrupt pending right after reset (#4449)
#36:Scheduled
master
2025-03-23 22:00:17 +08:00
0s
fix(difftest, CSR): sync non-reg interrupt pending right after reset (#4449)
#35:Scheduled
master
2025-03-23 15:33:15 +08:00
0s
feat: make `HART_ID_BITS` configurable in Makefile (#4432)
#33:Scheduled
master
2025-03-22 13:20:18 +08:00
0s
fix(fusion): block fusion when trigger fire and exception happen (#4439)
#30:Scheduled
master
2025-03-20 20:30:19 +08:00
0s
feat: mark topdown, cycle and instr as critical perf counters (#4431)
#27:Scheduled
master
2025-03-19 20:00:20 +08:00
0s
fix(DecodeUnit): add `II exception` to the `TileLink` of the cbo instr (#4430)
#25:Scheduled
master
2025-03-18 19:30:18 +08:00
0s
submodule(ready-to-run): Bump nemu ref in ready-to-run (#4416)
#22:Scheduled
master
2025-03-17 19:00:20 +08:00
0s
submodule(ready-to-run): Bump nemu ref in ready-to-run (#4416)
#21:Scheduled
master
2025-03-17 15:33:15 +08:00
0s
submodule(ready-to-run): Bump nemu ref in ready-to-run (#4416)
#20:Scheduled
master
2025-03-16 15:33:15 +08:00
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fix(L2TLB): Napot entries in LLPTW should not be compressed (#4396)
#16:Scheduled
master
2025-03-14 17:30:20 +08:00
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fix(Top): fix `l3Miss` interface connection (#4410)
#14:Scheduled
master
2025-03-14 01:10:20 +08:00
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submodule(CoupledL2): bump CoupledL2 (#4384)
#11:Scheduled
master
2025-03-12 16:30:18 +08:00
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fix(MainPipe): `DCache` meta is not changed when sc/cas fails (#4217)
#8:Scheduled
master
2025-03-11 16:00:19 +08:00
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fix(MainPipe): `DCache` meta is not changed when sc/cas fails (#4217)
#7:Scheduled
master
2025-03-11 15:33:15 +08:00
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feat(AIA): integrate ChiselAIA (#4378)
#4:Scheduled
master
2025-03-09 23:10:17 +08:00
0s
chore(scalastyle): allow sx_lowerCamelCase naming for pipeline signals
#2:Scheduled
master
2025-03-08 22:40:18 +08:00
0s