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Merge 90dbd0cb5b into 1e7e38e249

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zhaohong1988 2025-04-22 10:06:56 +08:00 committed by GitHub
parent 1e7e38e249 90dbd0cb5b
commit 2a87d92571
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1 changed files with 10 additions and 14 deletions
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24
src/main/scala/top/XSNoCTop.scala
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@ -33,10 +33,9 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.tilelink._
import coupledL2.tl2chi.{CHIAsyncBridgeSink, PortIO}
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.util.{AsyncQueueParams, AsyncQueueSource}
import freechips.rocketchip.util.{AsyncQueueParams, AsyncQueueSource, AsyncResetSynchronizerShiftReg}
import chisel3.experimental.{ChiselAnnotation, annotate}
import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
import difftest.common.DifftestWiring
import difftest.util.Profile
@ -208,24 +207,21 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
*/
val soc_rst_n = io.lp.map(_.i_cpu_sw_rst_n).getOrElse(true.B)
val soc_iso_en = io.lp.map(_.i_cpu_iso_en).getOrElse(false.B)
/* Core+L2 reset when:
1. normal reset from SoC
2. SoC initialize reset during Power on/off flow
*/
val cpuReset = reset.asBool || !soc_rst_n
val cpuReset_sync = withClockAndReset(clock, cpuReset)(ResetGen(2, io.dft_reset))
//Interrupt sources collect
val msip = clint.head(0)
val mtip = clint.head(1)
val meip = plic.head(0)
val seip = plic.last(0)
val nmi_31 = nmi.head(0)
val nmi_43 = nmi.head(1)
val debugIntr = debug.head(0)
val msi_info_vld = core_with_l2.module.io.msiInfo.valid
val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, debugIntr, msi_info_vld)
val msip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(clint.head(0), 3, 0)}
val mtip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(clint.head(1), 3, 0)}
val meip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(plic.head(0), 3, 0)}
val seip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(plic.last(0), 3, 0)}
val nmi_31 = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(nmi.head(0), 3, 0)}
val nmi_43 = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(nmi.head(1), 3, 0)}
val msi_info_vld = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(core_with_l2.module.io.msiInfo.valid, 3, 0)}
val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, msi_info_vld)
/*
* CPU Low Power State:
* 1. core+L2 Low power state transactions is triggered by l2 flush request from core CSR