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fix(LSU): misalign exception are generated directly within the pipeline (#4757)
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Previously, when accessing mmio space after splitting, we generated an
exception in misalignbuffer, which prevented the exception address from
being written to exceptionbuffer.
Therefore, we now choose to generate an exception in pipeline so that
the exception address can be written correctly.
This commit is contained in:
Anzo 2025-06-03 11:23:22 +08:00 committed by GitHub
parent 8769efd7b4
commit b4473bd3f0
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2 changed files with 2 additions and 2 deletions
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2
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
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@ -1314,7 +1314,7 @@ class LoadUnit(implicit p: Parameters) extends XSModule
// Here a judgement is made as to whether a misaligned exception needs to actually be generated.
// We will generate misaligned exceptions at mmio.
val s2_real_exceptionVec = WireInit(s2_exception_vec)
s2_real_exceptionVec(loadAddrMisaligned) := s2_out.isMisalign && s2_uncache
s2_real_exceptionVec(loadAddrMisaligned) := (s2_out.isMisalign || s2_out.isFrmMisAlignBuf) && s2_uncache
s2_real_exceptionVec(loadAccessFault) := s2_exception_vec(loadAccessFault) ||
s2_fwd_frm_d_chan && s2_d_corrupt ||
s2_fwd_data_valid && s2_fwd_frm_mshr && s2_mshr_corrupt

2
src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
View File

@ -477,7 +477,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule
s2_pmp.ld && s2_isCbo_noZero || // cmo need read permission but produce store exception
((s2_in.isvec || s2_isCbo) && s2_actually_uncache && RegNext(s1_feedback.bits.hit))
) && s2_vecActive
s2_out.uop.exceptionVec(storeAddrMisaligned) := s2_actually_uncache && s2_in.isMisalign && !s2_un_misalign_exception
s2_out.uop.exceptionVec(storeAddrMisaligned) := s2_actually_uncache && (s2_in.isMisalign || s2_in.isFrmMisAlignBuf) && !s2_un_misalign_exception
s2_out.uop.vpu.vstart := s2_in.vecVaddrOffset >> s2_in.uop.vpu.veew
// kill dcache write intent request when mmio or exception