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fix(vlbusytable): remove wakeUpInt to avoid load fast wakes up vsetvli (#4941)

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Ziyue Zhang 2025-08-14 15:15:33 +08:00 committed by GitHub
parent 7189933c87
commit ef913a6ad6
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1 changed files with 2 additions and 1 deletions
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src/main/scala/xiangshan/backend/rename/BusyTable.scala
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@ -88,7 +88,8 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int, numPhyPregs: Int, pregWB:
case FpWB(_, _) => allWakeUp.filter{x => x.bits.params.writeFpRf && !x.bits.params.hasLoadExu} case FpWB(_, _) => allWakeUp.filter{x => x.bits.params.writeFpRf && !x.bits.params.hasLoadExu}
case VfWB(_, _) => allWakeUp.filter(_.bits.params.writeVfRf) case VfWB(_, _) => allWakeUp.filter(_.bits.params.writeVfRf)
case V0WB(_, _) => allWakeUp.filter(_.bits.params.writeV0Rf) case V0WB(_, _) => allWakeUp.filter(_.bits.params.writeV0Rf)
case VlWB(_, _) => allWakeUp.filter(_.bits.params.writeVlRf) // avoid load fast wakes, since load cancel signal not connected to vlbusytable, may have bug for vsetvli
case VlWB(_, _) => allWakeUp.filter(x => false)
case _ => throw new IllegalArgumentException(s"WbConfig ${pregWB} is not permitted") case _ => throw new IllegalArgumentException(s"WbConfig ${pregWB} is not permitted")
} }
val loadDependency = RegInit(0.U.asTypeOf(Vec(numPhyPregs, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W))))) val loadDependency = RegInit(0.U.asTypeOf(Vec(numPhyPregs, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))))