31 Commits

Author	SHA1	Message	Date
Xu, Zefan	d1bdb5cb64	misc(submodule): correct case seneitivity in url (#4585) ... The repo url in Gitee is case sensitive. It's necessary to correct them.	2025-04-18 10:34:02 +08:00
Tang Haojin	8cfc24b284	feat(AIA): integrate ChiselAIA again (#4509)	2025-04-07 20:40:20 +08:00
Tang Haojin	529b1cfdb5	Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429) ... This reverts commit 7fbc1cb42a.	2025-03-17 20:17:45 +08:00
Tang Haojin	7fbc1cb42a	feat(AIA): integrate ChiselAIA (#4378)	2025-03-08 21:33:35 +08:00
Tang Haojin	720dd6218e	top: implement XSNoCTop and standalone devices (#3136)	2024-07-04 22:20:58 +08:00
zhanglinjuan	78a8cd257c	SoC: an initial version of DummyLLC	2024-07-03 16:25:01 +08:00
Xuan Hu	68d130856f	Merge remote-tracking branch 'upstream/master' into tmp-new-backend-merge-vlsu ... # Conflicts: # .gitmodules # build.sc # src/main/scala/top/Configs.scala # src/main/scala/xiangshan/Bundle.scala # src/main/scala/xiangshan/Parameters.scala # src/main/scala/xiangshan/XSCore.scala # src/main/scala/xiangshan/backend/CtrlBlock.scala # src/main/scala/xiangshan/backend/MemBlock.scala # src/main/scala/xiangshan/backend/Scheduler.scala # src/main/scala/xiangshan/backend/issue/ReservationStation.scala # src/main/scala/xiangshan/backend/issue/StatusArray.scala # src/main/scala/xiangshan/backend/rob/Rob.scala # src/main/scala/xiangshan/mem/MemCommon.scala # src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala # src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala # src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala # src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala # src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala	2023-05-25 16:50:12 +08:00
wakafa	15ee59e46c	Merge coupledL2 into master (#2064) ... * icache: Acquire -> Get to L2 * gitmodules: add coupledL2 as submodule * cpl2: merge coupledL2 into master * Changes includes: * coupledL2 integration * modify user&echo fields in i$/d$/ptw * set d$ never always-releasedata * remove hw perfcnt connection for L2 * bump utility * icache: remove unused releaseUnit * config: minimalconfig includes l2 * Otherwise, dirty bits maintainence may be broken * Known issue: L2 should have more than 1 bank to avoid compiling problem * bump Utility * bump coupledL2: fix bugs in dual-core * bump coupledL2 * icache: set icache as non-coherent node * bump coupledL2: fix dirty problem in L2 ProbeAckData --------- Co-authored-by: guohongyu <20373696@buaa.edu.cn> Co-authored-by: XiChen <chenxi171@mails.ucas.ac.cn>	2023-05-25 10:05:08 +08:00
ZhangZifei	b6c99e8e08	Merge remote-tracking branch 'origin/master' into rf-after-issue	2022-12-29 22:09:13 +08:00
ZhangZifei	e9cc9d5171	submodule: tmp change to .gitsubmodules for merge master	2022-12-29 21:41:35 +08:00
wakafa	3c02ee8f82	Separate Utility submodule from XiangShan (#1861) ... * misc: add utility submodule * misc: adjust to new utility framework * bump utility: revert resetgen * bump huancun	2022-12-25 14:52:31 +08:00
ZhangZifei	30056234ee	yunsuan: add yunsuan as a submodule ... YunSuan: OpenXiangShan/YunSuan YunSuan includes XiangShan's function units like: 1. vector exe unit 2. float points exe unit Some vector instruction like permutation will still stay at XiangShan for convenience.	2022-12-15 18:39:36 +08:00
Jiawei Lin	72060888ce	Clean up project dependencies (#1282) ... * Clean up project dependencies * Update README * Fix typo	2021-12-01 08:52:47 +08:00
Jiawei Lin	a1ea7f76ad	Use HuanCun instead of block-inclusive-cache (#1016) ... * misc: add submodule huancun * huancun: integrate huancun to SoC as L3 * remove l2prefetcher * update huancun * Bump HuanCun * Use HuanCun instead old L2/L3 * bump huancun * bump huancun * Set L3NBanks to 4 * Update rocketchip * Bump huancun * Bump HuanCun * Optimize debug configs * Configs: fix L3 bug * Add TLLogger * TLLogger: fix release ack address * Support write prefix into database * Recoding more tilelink info * Add a database output format converter * missqueue: add difftest port for memory difftest during refill * misc: bump difftest * misc: bump difftest & huancun * missqueue: do not check refill data when get Grant * Add directory debug tool * config: increase client dir size for non-inclusive cache * Bump difftest and huancun * Update l2/l3 cache configs * Remove deprecated fpga/* * Remove cache test * Remove L2 preftecher * bump huancun * Params: turn on l2 prefetch by default * misc: remove duplicate chisel-tester2 * misc: remove sifive inclusive cache * bump difftest * bump huancun * config: use 4MB L3 cache * bump huancun * bump difftest * bump difftest Co-authored-by: wangkaifan <wangkaifan@ict.ac.cn> Co-authored-by: TangDan <tangdan@ict.ac.cn>	2021-09-10 18:27:23 +08:00
Jiawei Lin	dc59782653	fudian: The new floating-point lib to replace hardfloat (#975) ... * Add submodule 'fudian' * IntToFP: use fudian * FMA: use fudian.CMA * FPToInt: remove recode format	2021-08-31 18:35:27 +08:00
William Wang	a3e876088a	Update difftest to use NEMU master branch (#902) ... misc: implement difftest as a submodule	2021-07-28 12:06:05 +08:00
Yinan Xu	f53115cba9	misc: cleanup for submodules and Makefile (#865) ... * misc: cleanup for submodules and Makefile * misc: use ready-to-run submodule Co-authored-by: William Wang <zeweiwang@outlook.com>	2021-07-05 16:37:11 +08:00
LinJiawei	59330107b0	.gitmodules: remove commit id	2021-01-13 16:14:06 +08:00
Lingrui98	34018581b4	added timingScripts as submodule	2021-01-13 00:57:38 +08:00
LinJiawei	77c5f3ecd9	update submodle 'block-inclusivecache'	2021-01-07 18:43:02 +08:00
LinJiawei	1a1319cb91	Merge branch 'origin/master' into hardfloat	2020-12-20 16:19:17 +08:00
BigWhiteDog	15d164019c	change rocket-chip submodule to one in RISCVERS repo	2020-12-09 21:40:10 +08:00
LinJiawei	01ff3fd1a6	Use XiangShan's port of 'berkeley-hardfloat'	2020-12-09 20:09:56 +08:00
LinJiawei	718a511df0	build.sc: do not use source of chisel3 and firrtl	2020-11-22 10:24:54 +08:00
Jiuyang liu	917276a097	rewrite build.sc to depend on chisel and firrtl by source.	2020-11-12 17:42:59 +00:00
LinJiawei	c5f31b5b1d	update chiseltest to 0.3.0	2020-10-28 11:40:21 +08:00
LinJiawei	106f28175b	update to chisel 3.4	2020-10-28 11:15:43 +08:00
BigWhiteDog	5fd452883b	change commit id for new l2 submodule branch	2020-10-21 22:12:15 +08:00
Allen	1a66c83d64	block-inclusive-cache: use our own copy of block-inclusive-cache. ... Changed sub module url and commit.	2020-10-21 16:59:32 +08:00
linjiawei	bf3210b97a	Add inclusivecache into git submodules	2020-08-25 11:57:19 +08:00
LinJiawei	2102afb52e	Import rocketchip into project	2020-08-12 12:56:20 +08:00