Zihao Yu
|
e7b8a81a2e
|
test,monitor: fix reset bug
|
2019-05-26 00:19:56 +08:00 |
|
Zihao Yu
|
cc08a75082
|
noop,IFU: add ibuf
|
2019-05-25 23:49:49 +08:00 |
Zihao Yu
|
c5a3122742
|
Merge pull request #31 from sashimi-yzh/update-fpga
Update fpga
|
2019-05-10 20:27:50 +08:00 |
|
Zihao Yu
|
81be003e46
|
board,zedboard: remove GPU
|
2019-05-10 20:25:43 +08:00 |
|
Zihao Yu
|
c357e0e172
|
fpga,zedboard: add monitor.v
|
2019-05-10 20:25:04 +08:00 |
|
Zihao Yu
|
355e85d908
|
remove GPU
|
2019-05-10 20:22:56 +08:00 |
|
Zihao Yu
|
bf6fe608e1
|
Merge pull request #30 from sashimi-yzh/verilator
Verilator
|
2019-05-10 19:07:16 +08:00 |
|
Zihao Yu
|
3d1cbb5b1c
|
clean up
|
2019-05-10 19:05:08 +08:00 |
|
Zihao Yu
|
13cfb810f6
|
implement keyboard and vga in emu
|
2019-05-10 18:54:19 +08:00 |
|
Zihao Yu
|
af5eab6138
|
move basic device handling to verilator by DPI
* TODO: implement keyboard and vga
|
2019-05-10 16:32:38 +08:00 |
|
Zihao Yu
|
0cba59648b
|
verilator,monitor: display instrCnt and cycleCnt
|
2019-05-10 15:40:27 +08:00 |
|
Zihao Yu
|
e8ab4e396e
|
verilator: support NOOPTrap
|
2019-05-10 14:18:21 +08:00 |
|
Zihao Yu
|
19dedbf619
|
add basic verilator build rules
|
2019-05-10 11:37:30 +08:00 |
|
Zihao Yu
|
caf5cfd6ff
|
Merge pull request #29 from sashimi-yzh/difftest
Difftest
|
2019-05-09 21:08:40 +08:00 |
|
Zihao Yu
|
bb6e93df21
|
difftest: skip MMIO
* FIXME: should also skip perfcnt CSR accessing
|
2019-05-09 20:56:51 +08:00 |
|
Zihao Yu
|
2d0149d76e
|
add basic difftest framework
|
2019-05-09 18:49:59 +08:00 |
|
Zihao Yu
|
76d60d431c
|
Merge pull request #28 from sashimi-yzh/gpu
Gpu
|
2019-03-04 21:31:20 +08:00 |
|
Zihao Yu
|
2017417da2
|
fpga,noop: reorganize interconnects
|
2019-03-03 23:38:28 +08:00 |
|
Zihao Yu
|
466a6a49d7
|
device,AXI4VGA: use 2 bit id for frame buffer
|
2019-03-03 23:36:40 +08:00 |
|
Zihao Yu
|
ba553cd98a
|
bus,axi4: make idBits configurable
|
2019-03-03 23:36:08 +08:00 |
|
Zihao Yu
|
40f96c68b1
|
device,AXI4VGA: use AXI4 for frame buffer to support burst write
|
2019-03-03 23:34:30 +08:00 |
|
Zihao Yu
|
873a5f9e31
|
gpu: support burst write
|
2019-03-03 23:31:18 +08:00 |
|
Zihao Yu
|
a72395f7e0
|
gpu: fix bug of unmatch read address
|
2019-03-03 23:29:58 +08:00 |
|
Zihao Yu
|
780164341b
|
gpu: rename waddr to wIdx to avoid conflict with AXI4Slave
|
2019-03-03 23:28:11 +08:00 |
|
Zihao Yu
|
da878e9ee1
|
Merge branch 'burst-cache' into gpu
|
2019-03-03 17:47:09 +08:00 |
|
Zihao Yu
|
00088a9849
|
Merge pull request #27 from sashimi-yzh/burst-cache
Burst cache
|
2019-03-03 17:40:19 +08:00 |
|
Zihao Yu
|
5a7b942b03
|
update sbt version
|
2019-03-03 16:54:26 +08:00 |
|
Zihao Yu
|
3735f2f62f
|
device,AXI4RAM: move assignments of rvalid and bvalid to AXI4Slave
|
2019-03-03 16:53:04 +08:00 |
|
Zihao Yu
|
e68f8385f3
|
device,AXI4RAM: support burst write
|
2019-03-03 15:50:41 +08:00 |
|
Zihao Yu
|
91b416b925
|
noop,Cache: support burst write
|
2019-03-03 15:49:55 +08:00 |
|
Zihao Yu
|
1941909b46
|
device,AXI4RAM: support burst read
|
2019-03-02 23:36:11 +08:00 |
|
Zihao Yu
|
0434e6d9d1
|
noop,Cache: support burst read
|
2019-03-02 23:35:18 +08:00 |
|
Zihao Yu
|
5945fcb3db
|
noop,Cache: use AXI4 master
|
2019-03-02 23:17:44 +08:00 |
|
Zihao Yu
|
f9ca23cdb3
|
gpu: support burst read for metaData channel
|
2019-03-02 18:44:53 +08:00 |
|
Zihao Yu
|
70a0b32835
|
fpga,noop: use interconnect to refactor axi connections
|
2019-03-02 17:25:51 +08:00 |
|
Zihao Yu
|
391d573844
|
gpu: split into two master ports
* also add a new uncached channel for GPU metadata
|
2019-03-02 17:24:40 +08:00 |
|
Zihao Yu
|
46253fc63e
|
fpga,zedboard: add gpu and run videotest successfully
|
2019-03-02 11:37:33 +08:00 |
|
Zihao Yu
|
97b7bc6cd5
|
test,NOOPTester: modify the address of framebuffer to match fpga
|
2019-03-02 11:35:33 +08:00 |
|
Zihao Yu
|
8541730c76
|
gpu: use AXI4 for the master port
|
2019-03-02 11:34:19 +08:00 |
|
Zihao Yu
|
2ebcf45920
|
device,AXI4Slave: add extra field to the bundle
|
2019-03-02 11:31:25 +08:00 |
|
Zihao Yu
|
4159428334
|
bus,axi4,AXI4: add dataBits as bundle parameter
|
2019-03-02 11:28:07 +08:00 |
|
Zihao Yu
|
499e8988a7
|
noop,NOOP: modify address space
|
2019-03-02 11:27:25 +08:00 |
|
Zihao Yu
|
20592feb00
|
device,AXI4RAM: do not write if the address is out-of-bound
|
2019-03-02 11:25:31 +08:00 |
|
Zihao Yu
|
59fcbda096
|
bus,simplebus,ToAXI4: use BoolStopWatch
|
2019-03-02 11:21:37 +08:00 |
|
Zihao Yu
|
ae1196cbab
|
Merge pull request #26 from sashimi-yzh/vga-ctrl
Vga ctrl
|
2019-03-01 20:00:44 +08:00 |
|
Zihao Yu
|
2b40c88236
|
test,top,SimMMIO: modify device address to match FPGA
|
2019-03-01 19:59:19 +08:00 |
|
Zihao Yu
|
8b16d27654
|
device,VGA: rename to AXI4VGA
|
2019-03-01 19:57:44 +08:00 |
|
Zihao Yu
|
0bba7889de
|
device,VGA: add VGA control registers
|
2019-03-01 19:47:52 +08:00 |
|
Zihao Yu
|
5c402924da
|
Merge pull request #25 from sashimi-yzh/refactor-axi
Refactor axi
|
2019-03-01 19:46:29 +08:00 |
|
Zihao Yu
|
c1364acfc2
|
bus,axi4: refactor code
|
2019-03-01 19:44:36 +08:00 |