11309 Commits

All Branches

Search

Author	SHA1	Message	Date
Anzooooo	bc84d3ccea	fix(simfrontend): fix execution flow errors caused by redirect	2025-09-30 10:52:44 +08:00
Yanqin Li	2c4a79ad7a	fix(prefetch): size of counter filter needs to add 1 (#5030)	2025-09-30 10:52:44 +08:00
HuSipeng	a6e745c484	fix(mbtb): fix parameterization of NumAlignBanks (#5052) ... support NumAlignBanks > 2	2025-09-29 11:48:35 +08:00
Zhihao Xu	ccc2ea946a	fix(ICache): stall read when updating (#5082) ... Fix kunminghu-v3 CI failure. In current design, when fence.i/flush/bus corrupt, the original assumption no longer holds.	2025-09-29 10:21:45 +08:00
zhanglinjuan	8d030f0833	misc: update CODEOWNERS (#5068)	2025-09-28 10:38:59 +08:00
Muzi	991afe5589	fix(resolve): adjust resolve queue parameter and branch enqueue index (#5050) ... Also delete unused ResolveQueueCommit.	2025-09-28 10:33:07 +08:00
Zhihao Xu	a9791a2b31	fix(ICache,Ifu): do not bpuFlush if not valid (#5072) ... Also: remove flushByStage2 as it doen't exists on V3 Bpu	2025-09-28 10:21:16 +08:00
lewislzh	03f5f93ab4	fix(Closecompress): when rob compress close, the brh instruction compress bit cannot be true	2025-09-27 15:23:39 +08:00
xiaofeibao	d15bd6440a	chore(fu): remove unused vfpu	2025-09-26 14:28:08 +08:00
xiaofeibao	e19b500ff1	feat(WbDataPath): optional generation of vldMgu	2025-09-26 14:28:08 +08:00
xiaofeibao	34629c5077	feat(DataPath): optional generation of regfile	2025-09-26 14:28:08 +08:00
xiaofeibao	0fe2018394	feat(region): remove IQResp cross region	2025-09-26 14:28:08 +08:00
sinceforYy	96e93a7941	fix(perfcct, ifu): fix enable for createInstMetaAtFetch	2025-09-26 10:09:48 +08:00
Zhang Xingyu	11e50ce495	feat(ibuffer): relax IBuffer enqueue condition (#5036) ... - `prevInstrCount` is equal to next cycle's `numFromFetch`, which calculated at ifu.s3, - compare `prevInstrCount` with next cycle's number of invalid entries (i.e. `numInvalidNext`), - the answer is next cycle's ready (NOT considering dequeue behavior and predChecker).	2025-09-25 18:00:12 +08:00
HuSipeng	6e87f33503	feat(Bpu): use first mispredict branch to train mbtb and tage (#5037) ... Co-authored-by: Anzooooo <anzoso@outlook.com>	2025-09-25 17:58:49 +08:00
Zhihao Xu	d860a548c5	fix(ICache): bpu s3 flush waylookup & mainPipe s1 (#5055) ... In v3 Ftq, we have `redirect` to Bpu and `redirectNext` to prefetch, therefore bp1=pf0. In this case, when an s1 prediction is overridden by s3, it can reach at most pf2/if1 (i.e. in prefetchPipe `s2` stage reg, wayLookup `entries(writePtr - 1)`, or mainPipe `s1` stage reg). In old design, we only flush pf1, that could be wrong. Though, we don't have to flush prefetchPipe s2, anyway it's prefetch and has no impact on control flow. (If we don't flush it, it can be seen as some sort of wrong-path prefetch). So, in this PR we implement wayLookup & mainPipe s1 flush from Bpu s3 override. NOTE: To reduce implementation cost, wayLookup assumes that we can flush at most 1 entry at tail, this could be wrong if we have Bpu s4/5/even more flush in the future. See comments there.	2025-09-25 17:58:31 +08:00
xiaofeibao	02022dc984	fix(forward): fix i2f wakeup fstore twice at same time	2025-09-25 16:00:19 +08:00
xiaofeibao	a2436eeb42	fix(wbArbiter): connect fpRegion write int regfile arbiter	2025-09-25 16:00:19 +08:00
xiaofeibao	3c36a1df4d	fix(dataPath): connect fp regfile read data to intRegion	2025-09-25 16:00:19 +08:00
xiaofeibao	a71a69df1a	fix(region): fix wrong stdIQEnq valid	2025-09-25 16:00:19 +08:00
xiaofeibao	3eb0037284	fix(bypassNetwork): connect fpEexuBlock out data to intRegion for store src	2025-09-25 16:00:19 +08:00
xiaofeibao	7fe2f46595	feat(backend): refactor module hierarchy for partiton	2025-09-25 16:00:19 +08:00
Yuandongliang	376ea68c64	fix(tage): connect WriteBuffer to Tage (#5056) ... WriteBuffer is connected to Tage By the way, remove the useless parameter hasTag from WriteBuffer	2025-09-25 11:09:18 +08:00
HuSipeng	58679724b1	fix(mbtb): filter out cross-page branches (#5060) ... When the some align bank is located on the next page,BPU may generate a cross-page fetch block. For example, [alignBank0, alignBank1], if alignBank1 located on the next page, and alignBank0 has no taken branch, alignBank1 has a taken branch, the fetch block which generated will be a cross-page fetch block.	2025-09-24 18:15:04 +08:00
HuSipeng	7b0395352d	fix(ifu): fix s1 flush condition (#5054)	2025-09-24 15:53:53 +08:00
Zhihao Xu	fb3831d68d	feat(ICache): remove mainPipe s2 stage (#5053)	2025-09-24 15:53:26 +08:00
xiaofeibao	100fa04895	feat(backend): connect isCall and isRet in reslove and redirect info to frontend	2025-09-24 15:13:58 +08:00
zhou tao	3c1962745b	fix(ifu): fix redirect path from IFU to return stack predictor.	2025-09-24 15:13:58 +08:00
HuSipeng	1bb82e92fd	feat(abtb): abtb SRAM change to 8 way (#5042)	2025-09-23 16:52:23 +08:00
HuSipeng	3813c8fd24	refactor(Bpu): now tage only output condTakenMask (#5045) ... TAGE should only be responsible for predicting the direction of conditional branches; therefore, it now only outputs condTakenMask instead of the takenMask for all branches.	2025-09-23 16:40:41 +08:00
Anzooooo	9a6e67e038	ci(perf): add performance tests for the simfrontend	2025-09-23 10:55:00 +08:00
Anzooooo	450925d014	feat(SimFrontend): implement the ideal front end for RTL	2025-09-23 10:55:00 +08:00
HuSipeng	72712cdf4e	fix(tage): fix x-state issue (#5043) ... In the previous code, the logic for training reads in the tables incorrectly overwrote the logic for prediction reads.	2025-09-22 18:49:07 +08:00
ngc7331	c36ed09eef	feat(Bpu): mask all branches after the first mispredicted ... also remove the unnecessary port train.firstMispredict, as all valid branches must be before first mispredict, and we have only one mispredict	2025-09-22 17:03:09 +08:00
ngc7331	643800297d	feat(CompareMatrix): add getLowerElementMask method	2025-09-22 17:03:09 +08:00
HuSipeng	c3d5b80404	fix(tage): table use Queue as write buffer (#5044) ... The current WriteBuffer is only suitable for writing one way at a time, but the tag table needs to write multiple ways at once. Therefore, we are temporarily using a Queue to buffer the write requests.	2025-09-22 14:45:09 +08:00
xiaofeibao	0306fb2bad	fix(robCompress): The new ftqOffset caused a bug in instruction fusion and Rob compression. Rob compression is temporarily turned off, and the number of Rob entries has increased from 160 to 224.	2025-09-22 10:32:39 +08:00
zhou tao	d59347f404	feat(ifu): adjust IFU calculation logic to align with instruction boundary changes.	2025-09-22 10:32:39 +08:00
Muzi	3f1be5f939	refactor(instr-boundary): rewrite boundary calculation	2025-09-22 10:32:39 +08:00
xu_zh	c8f6f6b7e6	misc(ci): increase swap & decrease JVM_XMX to avoid oom (#5038) ... Hopefully this will fix CI failure due to Upload Artifact (on GitHub hosted runner, with only 16G mem) OOM: <img width="858" height="88" alt="image" src="https://github.com/user-attachments/assets/1e78ce7f-49e5-4b1c-8f9d-41d74fdf52a9" /> Local analysis by jvisualvm shows we need 8.8G heap mem at peak (JVM_XMX=16G with default gc strategy), so maybe we can reduce JVM_MAX from 16G to 10G to trigger gc more frequently, and use less mem. And, we can clean up unused pre-installed tool to reclaim more space for swap (refer to https://github.com/actions/runner-images/issues/709#issuecomment-612569242), though we're utilizing `/mnt` now and it seems the disk space is already enough. Then we can increase swapfile size. Also: fix typo	2025-09-19 11:31:02 +08:00
ngc7331	2f019602df	feat(abtb): use fast train ... Also: fix that io.enable should control t0_valid Co-authored-by: xu_zh <ngc7331@outlook.com> Co-authored-by: HuSipeng <husipeng24@qq.com>	2025-09-19 10:20:57 +08:00
ngc7331	f5620a5d4a	feat(ubtb): add EnableFastTrain field & ubtb support fast train	2025-09-19 10:20:57 +08:00
zhou tao	8c11cfe0a1	fix(ftq): relax the gating of backendException. (#5035) ... Fix kunminghu-v3 CI failure: https://github.com/OpenXiangShan/XiangShan/actions/runs/17785701869/job/50552936980 - #5016	2025-09-18 10:13:14 +08:00
Yuandongliang	de5fdd22b0	fix(abtb): fix abtb meta signal X-Propagation (#5028)	2025-09-17 18:35:11 +08:00
Tang Haojin	ad7d606e59	feat(build): add `DISABLE_XMR` to use `bore` instead of `tapAndRead` (#4976)	2025-09-17 14:46:58 +08:00
Xin Tian	056d179c1c	fix(Bitmap): fix not need bitmap check logic in LLPTW (#5018) ... * add CSRs *PBMTE Mux logic for pte.isPf to use * add allStage condition for gStagePf	2025-09-17 14:46:58 +08:00
Yinan Xu	fe1ee5dd5b	fix(difftest): bump and align parseArg return values (#5009) ... * We also add the customized coverage firtool arguments	2025-09-17 14:46:58 +08:00
lwd	1965d9c98c	fix(Vsegment): fix address generation of misaligned split (#5006) ... during the `s_pm` state, we set `isMisalignReg` from `isMisalignWire`. Therefore, when `state === s_pm`, `isMisalignReg` has not yet been set, so we need to modify it to `isMisalignReg`.	2025-09-17 14:46:58 +08:00
Yanqin Li	d4a884d45b	fix(prefetch): the statistic of prefetch hit (#5005)	2025-09-17 14:46:58 +08:00
Haoyuan Feng	45593c185a	ci(config): set EnableSramCtl by default for lowpower (#5002)	2025-09-17 14:46:58 +08:00