Merge f908c054a9 into f9ed852fb2

fix(xiselect): set the minimum range for xiselect (#4594 )
The miselect register implements at least enough bits to support all implemented miselect values. The siselect register will support the value range 0..0xFFF at a minimum. The vsiselect register will support the value range 0..0xFFF at a minimum.
2025-04-22 10:01:00 +08:00 · 2025-04-22 09:52:44 +08:00 · 2025-04-22 00:42:41 +08:00 · 2025-04-22 00:42:07 +08:00 · 2025-04-22 00:40:40 +08:00 · 2025-04-22 00:37:45 +08:00
9 changed files with 44 additions and 55 deletions
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 6608dc16ec944800d39200e2fad5924d0968b42b
+Subproject commit eacee874c515eadfe197cd6b66a52799c30332c1
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit c22a4b2e81d97680380c38cb1ccc7cc2028f01fa
+Subproject commit 2b60fc5edf50f519a4310dc41620e9a204b4aacb
--- a/scalastyle-config.xml
+++ b/scalastyle-config.xml
@ -71,38 +71,38 @@
 <!-- always add a space after `//` or `/*` before comments -->
 <check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
 <!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- (, ~, ! -->
   <parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- :, ,, ) -->
   <parameter name="tokens">COLON, COMMA, RPAREN</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
   <parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
   <parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
   <parameter name="regex"><![CDATA[[^ ](:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)]]></parameter>
  </parameters>
  <customMessage>No space before operators</customMessage>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>
--- a/scalastyle-test-config.xml
+++ b/scalastyle-test-config.xml
@ -71,43 +71,43 @@
 <!-- always add a space after `//` or `/*` before comments -->
 <check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
 <!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- (, ~, ! -->
   <parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- :, ,, ) -->
   <parameter name="tokens">COLON, COMMA, RPAREN</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
   <parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
   <parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
   <parameter name="regex"><![CDATA[[^ ](:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)]]></parameter>
  </parameters>
  <customMessage>No space before operators</customMessage>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
-   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ ]]]></parameter>
+   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>
  </parameters>
-  <customMessage>No space after operators</customMessage>
+  <customMessage>No space or newline after operators</customMessage>
 </check>

 <!-- ===== imports ===== -->
@ -158,7 +158,7 @@
 <!-- pure lower cases for package names -->
 <check enabled="true" class="org.scalastyle.scalariform.PackageNamesChecker" level="warning">
  <parameters>
-   <parameter name="regex">^[a-z]*$</parameter>
+   <parameter name="regex">^[a-z0-9]*$</parameter>
  </parameters>
 </check>

--- a/src/main/scala/top/XSNoCTop.scala
+++ b/src/main/scala/top/XSNoCTop.scala
@ -222,8 +222,9 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
    val seip  = plic.last(0)
    val nmi_31 = nmi.head(0)
    val nmi_43 = nmi.head(1)
+    val debugIntr = debug.head(0)
    val msi_info_vld = core_with_l2.module.io.msiInfo.valid
-    val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, msi_info_vld)
+    val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, debugIntr, msi_info_vld)

    /*
     * CPU Low Power State:
--- a/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
+++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
@ -204,11 +204,11 @@ class ISelectField(final val maxValue: Int, reserved: Seq[Range]) extends CSREnu
 }

 object VSISelectField extends ISelectField(
-  0x1FF,
+  0xFFF,
  reserved = Seq(
    Range.inclusive(0x000, 0x02F),
    Range.inclusive(0x040, 0x06F),
-    Range.inclusive(0x100, 0x1FF),
+    Range.inclusive(0x100, 0xFFF),
  ),
 )

@ -221,15 +221,16 @@ object MISelectField extends ISelectField(
 )

 object SISelectField extends ISelectField(
-  maxValue = 0xFF,
+  maxValue = 0xFFF,
  reserved = Seq(
-    Range.inclusive(0x00, 0x2F),
-    Range.inclusive(0x40, 0x6F),
+    Range.inclusive(0x000, 0x02F),
+    Range.inclusive(0x040, 0x06F),
+    Range.inclusive(0x100, 0xFFF),
  ),
 )

 class VSISelectBundle extends CSRBundle {
-  val ALL = VSISelectField(log2Up(0x1FF), 0, null).withReset(0.U)
+  val ALL = VSISelectField(log2Up(0xFFF), 0, null).withReset(0.U)
 }

 class MISelectBundle extends CSRBundle {
@ -237,7 +238,7 @@ class MISelectBundle extends CSRBundle {
 }

 class SISelectBundle extends CSRBundle {
-  val ALL = SISelectField(log2Up(0xFF), 0, null).withReset(0.U)
+  val ALL = SISelectField(log2Up(0xFFF), 0, null).withReset(0.U)
 }

 class TopIBundle extends CSRBundle {
--- a/src/main/scala/xiangshan/backend/rename/Rename.scala
+++ b/src/main/scala/xiangshan/backend/rename/Rename.scala
@ -206,8 +206,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
  private val inst         = Wire(Vec(RenameWidth, new XSInstBitFields))
  private val isCsr        = Wire(Vec(RenameWidth, Bool()))
  private val isCsrr       = Wire(Vec(RenameWidth, Bool()))
-  private val isWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
-  private val isBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
+  private val isNotWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
+  private val isNotBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
  private val fuType       = uops.map(_.fuType)
  private val fuOpType     = uops.map(_.fuOpType)
  private val vtype        = uops.map(_.vpu.vtype)
@ -291,9 +291,9 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
    inst(i) := uops(i).instr.asTypeOf(new XSInstBitFields)
    isCsr(i) := inst(i).OPCODE5Bit === OPCODE5Bit.SYSTEM && inst(i).FUNCT3(1, 0) =/= 0.U
    isCsrr(i) := isCsr(i) && inst(i).FUNCT3 === BitPat("b?1?") && inst(i).RS1 === 0.U
-    isWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
+    isNotWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
      inst(i).CSRIDX, true.B, CSROoORead.waitForwardInOrderCsrReadList.map(_.U -> false.B))
-    isBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
+    isNotBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
      inst(i).CSRIDX, true.B, CSROoORead.blockBackwardInOrderCsrReadList.map(_.U -> false.B))

    /*
@ -303,8 +303,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     *
     * Signal "isCsrr" contains not only "CSRR", but also other CSR instructions that do not require writing to CSR.
     */
-    uops(i).waitForward := io.in(i).bits.waitForward && !isWaitForwardCsrr(i)
-    uops(i).blockBackward := io.in(i).bits.blockBackward && !isBlockBackwardCsrr(i)
+    uops(i).waitForward := io.in(i).bits.waitForward && !isNotWaitForwardCsrr(i)
+    uops(i).blockBackward := io.in(i).bits.blockBackward && !isNotBlockBackwardCsrr(i)

    // update cf according to ssit result
    uops(i).storeSetHit := io.ssit(i).valid
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
@ -300,7 +300,7 @@ class LoadQueue(implicit p: Parameters) extends XSModule
  for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) {
    // from load_s3
    val ldinBits = io.ldu.ldin(w).bits
-    buff.valid := io.ldu.ldin(w).valid && (ldinBits.nc || ldinBits.mmio) && !ldinBits.rep_info.need_rep && !ldinBits.nc_with_data
+    buff.valid := io.ldu.ldin(w).valid && !ldinBits.nc_with_data
    buff.bits := ldinBits
  }

--- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
@ -1132,35 +1132,22 @@ class StoreQueue(implicit p: Parameters) extends XSModule
    // Vector instructions that prevent triggered exceptions from being written to the 'databuffer'.
    val vecHasExceptionFlagValid = vecExceptionFlag.valid && isVec(ptr) && vecExceptionFlag.bits.robIdx === uop(ptr).robIdx

+    val misalignToDataBufferValid = allocated(rdataPtrExt(0).value) && committed(rdataPtrExt(0).value) &&
+                                    (!isVec(rdataPtrExt(0).value) && allvalid(rdataPtrExt(0).value) || vecMbCommit(rdataPtrExt(0).value)) &&
+                                    canDeqMisaligned && (!isCross4KPage || isCross4KPageCanDeq || hasException(rdataPtrExt(0).value))
    // Only the first interface can write unaligned directives.
    // Simplified design, even if the two ports have exceptions, but still only one unaligned dequeue.
    val assert_flag = WireInit(false.B)
    when(firstWithMisalign && firstWithCross16Byte) {
-      dataBuffer.io.enq(0).valid := canDeqMisaligned && allocated(rdataPtrExt(0).value) && committed(rdataPtrExt(0).value) &&
-        ((!isVec(rdataPtrExt(0).value) && allvalid(rdataPtrExt(0).value) || vecMbCommit(rdataPtrExt(0).value)) &&
-        (!isCross4KPage || isCross4KPageCanDeq) || hasException(rdataPtrExt(0).value)) && !ncStall
-
-      dataBuffer.io.enq(1).valid := canDeqMisaligned && allocated(rdataPtrExt(0).value) && committed(rdataPtrExt(0).value) &&
-        (!isVec(rdataPtrExt(0).value) && allvalid(rdataPtrExt(0).value) || vecMbCommit(rdataPtrExt(0).value)) &&
-        (!isCross4KPage || isCross4KPageCanDeq) && !hasException(rdataPtrExt(0).value) && !ncStall
+      dataBuffer.io.enq(i).valid := misalignToDataBufferValid
      assert_flag := dataBuffer.io.enq(1).valid
    }.otherwise {
-      if (i == 0) {
-        dataBuffer.io.enq(i).valid := (
-          allocated(ptr) && committed(ptr)
-            && ((!isVec(ptr) && (allvalid(ptr) || hasException(ptr))) || vecMbCommit(ptr))
-            && !mmioStall && !ncStall
-            && (!unaligned(ptr) || !cross16Byte(ptr) && (allvalid(ptr) || hasException(ptr)))
-          )
-      }
-      else {
-        dataBuffer.io.enq(i).valid := (
-          allocated(ptr) && committed(ptr)
-            && ((!isVec(ptr) && (allvalid(ptr) || hasException(ptr))) || vecMbCommit(ptr))
-            && !mmioStall && !ncStall
-            && (!unaligned(ptr) || !cross16Byte(ptr) && (allvalid(ptr) || hasException(ptr)))
-          )
-      }
+      dataBuffer.io.enq(i).valid := (
+        allocated(ptr) && committed(ptr)
+          && ((!isVec(ptr) && (allvalid(ptr) || hasException(ptr))) || vecMbCommit(ptr))
+          && !mmioStall && !ncStall
+          && (!unaligned(ptr) || !cross16Byte(ptr) && (allvalid(ptr) || hasException(ptr)))
+        )
    }

    val misalignAddrLow = vaddrModule.io.rdata(0)(2, 0)
Author	SHA1	Message	Date
Anzo	c45d6d5834	Merge `f908c054a9` into `f9ed852fb2`	2025-04-22 10:01:00 +08:00
NewPaulWalker	f9ed852fb2	fix(xiselect): set the minimum range for xiselect (#4594 ) The miselect register implements at least enough bits to support all implemented miselect values. The siselect register will support the value range 0..0xFFF at a minimum. The vsiselect register will support the value range 0..0xFFF at a minimum.	2025-04-22 09:52:44 +08:00
cz4e	99a48a761c	timing(LoadQueueUncache): adjust s1 enq and s2 enq valid generate logic (#4603 ) EMU Test / Changes Detection (push) Waiting to run Details EMU Test / Generate Verilog (push) Blocked by required conditions Details EMU Test / EMU - Basics (push) Blocked by required conditions Details EMU Test / EMU - CHI (push) Blocked by required conditions Details EMU Test / EMU - Performance (push) Blocked by required conditions Details EMU Test / EMU - MC (push) Blocked by required conditions Details EMU Test / SIMV - Basics (push) Blocked by required conditions Details EMU Test / Upload Artifacts (push) Blocked by required conditions Details EMU Test / Check Submodules (push) Blocked by required conditions Details EMU Test / Check Format (push) Blocked by required conditions Details	2025-04-22 00:42:41 +08:00
Anzo	cd450e3243	submodule(ready-to-run): bump nemu and spike ref in ready-to-run (#4604 )	2025-04-22 00:42:07 +08:00
Zhaoyang You	51ad03b0f6	fix(rename): fix Csrr format (#4605 )	2025-04-22 00:40:40 +08:00
zhaohong1988	d7dd2491d4	submodule(ChiselAIA): bump ChiselAIA (#4595 )	2025-04-22 00:37:45 +08:00
xu_zh	be3685ffd1	chore(scalastyle): disable space-around-operator checks (#4567 )	2025-04-22 00:37:04 +08:00
Guanghui Cheng	b5c820f608	fix(top): enable cpuclock when debug halt req (#4583 )	2025-04-22 00:36:20 +08:00
Anzooooo	f908c054a9	fix(StoreQueue): fix misalign's Databuffer enq logic	2025-04-21 16:44:33 +08:00