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Author	SHA1	Message	Date
Jiuyue Ma	2f33bcee09	refactor(XSNoCTop): Separate BaseXSSocImp base class and HasAsyncClockImp trait ... This commit separate IO, clock and reset out of XSNoCTop class. Specifically, IO and basic clock/reset are moved to BaseXSSocImp base class. The sync clock/reset (a.k.a. noc_, soc_) are moved to HasAsyncClockImp. Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>	2025-05-28 11:51:38 +08:00
CharlieLiu	54b6c3b665	fix(DCache): fix clock gating enable for s3_error in MainPipe (#4744) ... Clock gating for `s3_error` in MainPipe should be enabled by `s2_fire_to_s3`, now fix it.	2025-05-28 11:29:12 +08:00
Guanghui Cheng	a51053205f	fix(trace): move checking xret from commit to rename (#4736)	2025-05-28 10:15:02 +08:00
Jiuyue Ma	a26390ca47	refactor(XSNoCTop): Move LowPower logic to trait method buildLowPower() (#4708) ... Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>	2025-05-27 10:57:55 +08:00
cz4e	7d5f3fc85b	fix(DCache): use `ParallelPrioirtyMux` instead of `ParallelMux` (#4737) ... * When there are multiple errors，`Mux1H` is equivalent to using `|`, for example * error 0, valid = 1, addr0 = 0x1000 * error 1, valid = 1, addr1 = 0x0ffff * the result is `io.error.valid == 1`, but `io.error.bits.addr == (addr0 | addr1)`, cause `ParallelMux` will generate circuit like this: ``` addr = (valid0 ? addr0 : 'h0) | (valid1 ? addr1 : 'h0) ``` * This problem can be avoided by using `ParallelPrioirtyMux` * adjust `MainPipe` error priority to highest	2025-05-27 10:41:56 +08:00
Anzo	9154cf341e	fix(StoreUnit): mask for the cmo instr is 0xFFFF (#4730) ... The cmo (mainly zero) instructions require the mask to be set to 0xFFFF (fully valid) in storeunit for forwarding and checking. This has to do with the storequeue's forwarding mechanism, where the storequeue passes through the mask to pre-pass data after an address match. For cmo instructions, the address will be matched by cacheline, so you need to set mask all to 1.	2025-05-26 20:56:49 +08:00
zhaohong1988	2dd61d9808	submodule(ChiselAIA):bump ChiselAIA to fix lose interrupt (#4732)	2025-05-26 19:44:38 +08:00
Tang Haojin	1a5f716e97	fix(ResetGen): sync 3 cycles by default (#4733)	2025-05-26 18:36:51 +08:00
Anzo	872d75c4d4	fix(VMergeBuffer): debug mode is also treated as an exception (#4707) ... Triggers include debug mode and breakpoint exceptions. The breakpoint exception will be in the exceptionVec, so no additional processing is required. Whereas debug mode is encoded in the signal trigger, when the trigger is set to debug mode, the processor should respond as if it were an exception, except that it will go into debug mode instead of an exception.	2025-05-26 14:44:13 +08:00
Yanqin Li	91fd9f11b8	submodule(CoupledL2): bump for longer BOP DQ latency (#4722) ... Since the latency from L2 to DDR is much higher in NoC scenarios, it is necessary to increase the `DelayQueue` latency of BOP to ensure timeliness.	2025-05-26 14:40:08 +08:00
cz4e	ed4ddc44a8	refactor(Config): refactor `DFT` option passing method (#4643) ... * Refactor `DFT` option passing method by `DFTOptionsKey` * `DFX` and `DFTOptionsKey.EnableMbist` are related. e.g. `DFX=1` equal to `DFTOptionsKey.EnableMbist=true` * `SRAM_WITH_CTL` and `DFTOptionsKey.EnableSramCtl` are related. e.g. `SRAM_WITH_CTL=1` equal to `DFTOptionsKey.EnableSramCtl=1` * `DFTOptionsKey.EnableMbist=true` by default **!!!Attention!!!** * `EnableMbist=true` and `EnableSramCtl=true`: support * `EnableMbist=true` and `EnableSramCtl=false`: support * `EnableMbist=false` and `EnableSramCtl=true`: it needs bump latest `Utility` for submodules, which references `Utility` * `EnableMbist=false` and `EnableSramCtl=false`: support	2025-05-26 11:15:45 +08:00
Guanghui Cheng	c56951d3e3	fix(sstateenx): generate sstateen[1|2|3]Module to verilog (#4723) ... The final result of both approaches is read-only 0, but in the former case, ssstateen[1|2|3] will be optimized away during Verilog generation, while in the latter case, it is preserved in the form shown in the diagram below. This has no impact on the actual circuit. 	2025-05-26 10:24:39 +08:00
Tang Haojin	619f5a5453	fix(jump, branch): fix wrong pc sext when sv48x4 (#4728)	2025-05-26 10:24:08 +08:00
cz4e	0c5bc3ba01	fix(LoadPipe): fix `prefetch_w` btot stall (#4729) ... Bug descritpions: * When there is a cacheline with `B` permission in DCache, and the `LoadPipe` execute `prefetch_w` requires BtoT, if there are 3 `BtoT`s in `MissQueue` at this time, this miss will still enter `MissQueue`. How to fix: * When a `BtoT` request appears in `LoadPipe`, it is necessary to confirm with `MissQueue` that the number of `BtoT` requests in the same set is less than `nWays - 1(3)`.	2025-05-25 18:38:00 +08:00
Haoyuan Feng	10ff24df82	fix(PMA): sc / amo should report af when !atomic (#4724)	2025-05-24 12:47:15 +08:00
cz4e	e494448356	fix(MainPipe): only requests from sbuffer are allowed to return replay response (#4720) ... Bug desciptions: * when the request from `MissQueue` occur `BtoT` fail (in fact, the request sent from `MissQueue` does not need to be check), `MainPipe` will response a replay to sbuffer, at the same time, hit response will sent to sbuffer too. How to fix: * In the case of `BtoT` fail, only requests from sbuffer are allowed to return replay response.	2025-05-22 18:59:18 +08:00
happy-lx	9e1cdd2f9b	perf(L1StreamPf): double the L2 prefetch distance (#4714) ... This PR change stream prefetcher L2 distance from 128 to 256 blocks. Since the latency from L2 to DDR is much higher in NoC scenarios, it is necessary to increase the L2 prefetch distance of stream prefetcher to ensure timeliness.	2025-05-22 15:59:25 +08:00
Yanqin Li	9d5c7d1ed3	fix(Uncache): add bus error handle for uncache store (#4717)	2025-05-22 15:58:48 +08:00
Jiuyue Ma	72fdab549b	refactor(XSNoCTop): Inherit XSNoCDiffTop from XSNoCTop instead composite (#4709) ... Use inherit instead of composite to reduce redundant IO port definitions and connections. At the same time, we are able to keep the original module name `XSTop` unchanged. Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>	2025-05-22 15:17:39 +08:00
Jiuyue Ma	e058d30117	fix(build): Always re-generated test-jar target by mill ... - leave the source dependency tracking work to mill - separate assembly and dest copy cmds to fix `make test-jar` output Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>	2025-05-22 15:12:45 +08:00
Jiuyue Ma	9e614723ac	fix(docker): Fix docker "-e" param when MAKEOVERRIDES contains space ... Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>	2025-05-22 15:12:45 +08:00
cz4e	122a4bb655	fix(MainPipe): fix pseudo ecc inject report address (#4718) ... Bug descriptions: When `MissQueue` refills data, ECC error injection occurs. The way where the tag hits before the ECC error is injected (if any) should be selected for replacement. However, `s1_need_replacement` does not take this into account, resulting in the error tag reported to `BEU` being the one selected by the replacer, rather than the tag corresponding to the ECC error injection. How to fix: * In the `s1` stage of `MainPipe`, add a check to determine whether it is in the ECC injection state. If so, it is necessary to determine whether to compare with the non-injected tag, determine whether there is a hit way, and select the hit way as the path corresponding to accessing `BankedDataArray`. * In the `s2` stage of `MainPipe`, by determining whether it is in the ECC injection state and whether there is a hit way with a tag error, add additional logic to indicate whether `replacement` or `eviction` really needs to be processed.	2025-05-22 15:02:40 +08:00
yulightenyu	103883845d	fix: safe protection before entering of WFI (backend/ifu/mmu/lsu) (#4691) ... fix: add safe protection according to the original semantics of WFI * This fix tries to solve the unsafe scenario where the Core is in the 'WFI' state, but there are still unfinished L2 transactions coming from IFU/MMU/LSU, which violates the original semantics of WFI. So, this protection was designed to guarantee that there are no pending requests to L2 before the Core enters the 'WFI' state. * The BE (Backend) actively initiates the reqWfi=1 signal to notify the IFU/MMU/LSU that the Core wants to enter WFI. * For IFU/MMU/LSU, when reqWfi=1, they stop sending all requests to L2. After all pending requests are completed, they send a safe=1 signal back to BE. * If an interrupt occurs while BE is waiting for the safe signal, it directly pulls reqWfi=0 to notify IFU/MMU/LSU that they do not need to enter the safe state, and BE automatically ends. At the same time, if IFU/MMU/LSU discover reqWfi=0 while waiting for pending requests, they remove the restriction on sending requests to L2 and pull the safe signal low. * The writeBack request from LSU to L2 is NOT included in this safe handshake protocol, because in the multi-core non-low-power WFI scenario, there may be a snoop from another Core to the 'WFI' Core. In this case, this writeback channel should be ACTIVE to respond to this snoop. However, in the low-power 'WFI' state, the 'WFI' Core will exit coherency before power down, so there will be no this kind of snoop. * To avoid timing iteration, each wfiSafe from ifu/mmu/lsu is registered before send to BE * Currently, this feature is fixed and verified by all regression tests on PLDM --------- Co-authored-by: chengguanghui <wissycgh@gmail.com> Co-authored-by: ngc7331 <ngc7331@outlook.com> Co-authored-by: sfencevma <15155930562@163.com> Co-authored-by: good-circle <fenghaoyuan19@mails.ucas.ac.cn>	2025-05-22 00:11:36 +08:00
zhanglinjuan	8104e33d37	submodule, perf, area(CoupledL2): bump CoupledL2 (#4715)	2025-05-22 00:10:24 +08:00
Anzo	cb82c8b8e2	fix(StoreQueue): redirect logic for vector exception (#4711) ... In this pr(https://github.com/OpenXiangShan/XiangShan/pull/4660), we introduce additional logic for redirect on vector exceptions. Previously, it was because, when `vecExceptionFlag` was high, we would need to wait for `lastflow` deq, in order to clear `vecExceptionFlag`, so we might need to prevent this one instruction from being flushed. --- However, with the previous modification, when a vector store has not yet deq, but needs to redirect itself, it will fail to cancel due to the use of `isAfter`. This leads to ptr exceptions in the storequeue, which can lead to stuckness. --- The solution, which has always been simple, is to prevent canceling itself only when the exception's directive deqs, i.e., when `vecExceptionFlag` is set.	2025-05-21 14:48:34 +08:00
Anzo	0390f4d1ff	fix(StoreUnit): cbo requires read permission (#4702) ... According to the manual description, cbo instr (inval clean flush) requires read permission but throws store exception. Considering that NEMU has multiple commits for other content modifications, I'll mention a separate bump NEMU pr	2025-05-21 14:47:33 +08:00
zhanglinjuan	92a95fb4d8	submodule(CoupledL2): bump CoupledL2 (#4710) ... This pr includes: - https://github.com/OpenXiangShan/CoupledL2/pull/412	2025-05-21 10:10:36 +08:00
Jiuyue Ma	13b80e32cf	feat(top): Move DTS ResourceBinding flow to BaseXSSoC (#4669) ... There are two independent SoC designs in XiangShan (a.k.a. `XSTop` and `XSNoCTop`), each containing its own DTS generation logic. This PR merges them into common base class `BaseXSSoc` and a specialized `HasDTSImp` trait, to prevent modifications to this part from being missed in different designs. --------- Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>	2025-05-21 09:52:31 +08:00
Anzo	8f200f145e	submodule(ready-to-run): bump nemu and NEMU ref in ready-to-run (#4705) ... Bump nemu ref in ready-to-run * NEMU commit:afd738be8ddcbe0c772a3a0658e48a735d54690b * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig * riscv64-xs-ref-debug_defconfig * riscv64-dual-xs-ref-debug_defconfig * riscv64-xs-ref_bitmap_defconfig Including: * fix(cbo): cbo requires read permission but throws store exception * fix(xtopi): when csrr xtopi, the old value of xtopi is read in some case * fix(xtopei): when csrrw xtopei, the old value of xtopei is read * fix(xtopi,difftest): update m/stopi when sync aia * fix(csr): mask the 0, 4 and 8 interrupt number of m/siprios	2025-05-20 16:03:14 +08:00
Yanqin Li	076c8dd2db	fix(NCMM): nc access in main memory should not skip difftest (#4704) ... **Bug Trigger:** In a self-modifying program, the program modifies its own instructions in a region where PBMT=NC and PMA=MM. If difftest is skipped in this case, NEMU will not execute the corresponding memory access instruction. This causes NEMU and DUT to execute different instructions later on, ultimately leading to an error. **Solution:** For regions where PBMT=NC and PMA=MM, difftest should not be skipped, since PMA=MM indicates that NEMU can perform normal synchronization. However, for regions with PMA=IO, difftest should still be skipped because NEMU might not be able to access the corresponding devices. Instruction self-modification in PMA=IO regions is generally not a concern, as such regions are typically non-writable. Therefore, synchronization of self-modifying IO instructions is not handled here (as doing so would be overly complex).	2025-05-20 16:02:04 +08:00
Qiming Chu	5019334cea	docs(README): update output files in generate verilog section (#4657) ... Since we use the `--split-verilog` option and MFC, the elaborator will generate multiple System Verilog files.	2025-05-20 14:54:52 +08:00
Yanqin Li	3c8fe1e213	fix(StoreQueue): not do nc store when having exception (#4661) ... ### Bug Description The NC store does not handle exceptions properly. When an exception occurs during its execution, the store queue (SQ) continues to process it as if it were a normal nc store—this includes committing it and sending it to the uncache—resulting in an invalid memory access. ### Bug Analysis In the current SQ design, for regular stores, both `rdataPtr` and `deqPtr` advance based on handshakes with `dataBuffer` and `SBuffer`, respectively. Thus, even if an exception occurs, the store is marked as `committed = true` and passed into both buffers. If an exception is detected at the `SBuffer`, the actual write is skipped. For NC stores, the `committed` logic is reused from regular stores. However, there is no dedicated handling for exceptional cases in the later pipeline stages—such as preventing handshake with the `UBuffer`, or allowing the handshake but skipping the write. This fix adopts the former approach: **NC stores will not perform a handshake with the `UBuffer` when an exception is detected**, in order to preserve a clean and consistent `UBuffer` interface. ### Solution * NC stores continue to be marked as `committed = true`. * Only when `!completed(rptr0) && allvalid(rptr0) && !hasException(rptr0)` is satisfied, the NC store is allowed to enter the `UBuffer`. * If the instruction causes an exception, the backend will flush it and all subsequent instructions. * When the flushed instruction reaches the NC store entry in the store queue, `completed` is set to `true`. * For `deqPtr`, since `deqPtr` advances based on the `completed` signal, no additional changes are needed. * For `rdataPtr`, behavior remains unchanged for regular stores, but for NC stores, advancement is now triggered by `completed` instead of `ncReadNextTrigger`.	2025-05-19 18:51:33 +08:00
Anzo	f96455c94b	fix(LSU): misaligned exception addr should use split addr (#4701) ... In this pr #4673, we set `fullva` incorrectly. `fullva` will be overridden by `tlb.resp.bits.fullva` again in a later stage. So we should set `fullva` in `s1_out` instead of `s0_out`.	2025-05-19 13:45:13 +08:00
Yanqin Li	3f0b442e26	fix(LoadQueueUncache): return origin data in LoadQueueUncache. (#4703) ... **Bug Trigger:** When the data responsed by `Uncache` is 0x0013 xxxx xxxx xxxx, the selected data handled by `LoadQueueUncache` is `0x0000 0000 0000 0013` in which case that `raddr(2, 0)` is 0b110 and `LSUOpType` is `lhu`. And this data is what we want. However it is then processed by the LoadUnit again with the same process and a new data `0x0000 0000 0000 0013` is obtained, which is error. So here needs to return origin data which will be selected in LoadUnit.	2025-05-19 13:37:53 +08:00
xu_zh	7894f4f93a	misc(ci): write IPC to GITHUB_STEP_SUMMARY (#4700) ... As an alternative to XiangShanRobot This will be helpful when we want to compare any two of CI runs, instead of just latest runs on PR & master Showcase: https://github.com/OpenXiangShan/XiangShan/actions/runs/15086713467?pr=4700	2025-05-19 10:40:44 +08:00
chengguanghui	6ff5d528c6	submodule(ready-to-run): bump ready-to-run to add context CSRs	2025-05-16 13:33:45 +02:00
chengguanghui	e60c537633	fix(csr): add `[m|h|s]context` for sdtrig extension	2025-05-16 13:33:45 +02:00
Zhaoyang You	2ab230db34	fix(csr): CSRR instruction read xtopi/xtopei inOrder (#4698)	2025-05-16 13:26:50 +02:00
zhanglinjuan	9bcab086b4	submodule(CoupledL2): bump CoupledL2 (#4697) ... This pr includes: - https://github.com/OpenXiangShan/CoupledL2/pull/399	2025-05-16 13:21:11 +02:00
Haoyuan Feng	8c4b481b90	fix(TLB): valididx(i) should all be true when isSuperPage (#4694) ... When the L2 TLB returns a PTW result to L1 TLB, if virtualization is enabled (including onlyS1, onlyS2, and allStage modes), then even when a huge page is accessed, only one entry in valididx(i) is marked as true. During the refill of the L1 TLB into TLBStorage, in the case of large pages, all valididx(i) entries should be manually set to true to ensure proper hit matching during subsequent lookups. However, in the previous design, this handling was only applied to address translations in onlyS2 mode. In fact, regardless of which virtualization translation mode is active, if a large page is accessed, all valididx(i) entries should be set to true. This commit fixes the bug.	2025-05-16 13:17:16 +02:00
zhaohong1988	ccd75ed114	submodule(ChiselAIA): bump ChiselAIA (#4693)	2025-05-16 13:16:59 +02:00
xiaofeibao-xjtu	ce863eb347	fix(rob): fix highDeqPtrMax from RobSize.U to (RobSize-1).U (#4690)	2025-05-16 13:16:20 +02:00
chengguanghui	ef67ee21f0	submodule(ready-to-run): bump ready-to-run to fix smstateen	2025-05-16 09:04:20 +02:00
chengguanghui	a0d02cd00f	fix(smstateen): add [m|h|s]stateen[1|2|3] CSRs ... * add [m|h|s]stateen[1|2|3] CSRs. * only reset mstateen[0|1|2|3] when init. * Bits in any stateen CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that hart.	2025-05-16 09:04:20 +02:00
Anzo	71d34cc3d2	fix(StoreQueue): cbozero flag should not be set on exception (#4663) ... Only if there are no exceptions, cbozero is allowed to set the status bits inside the storequeue and write back through the storequeue. When there is an exception, write back directly through storeunit.	2025-05-16 10:57:18 +08:00
linzhida	04a46b4e7a	submodule(ready-to-run): Bump nemu ref in ready-to-run ... * NEMU commit:d7f606977161a50dc03857976916e2576b3bf9ea * NEMU configs: * riscv64-xs-ref_defconfig * riscv64-dual-xs-ref_defconfig * riscv64-xs-ref-debug_defconfig * riscv64-dual-xs-ref-debug_defconfig * riscv64-xs-ref_bitmap_defconfig Including: * refactor(priv): split priv_instr() into several functions * refactor(fence.i): set flush flag directly * refactor(mop): simplify the decode and exec helper * refactor(priv): totally abandon rtl_sys_slow_path * fix(Smstateen): add missing Smstateen permission checks * feat(Smcsrind): implement Smcsrind extension and enable it.	2025-05-15 15:07:48 +02:00
linzhida	8c37302846	submodule(rocket-chip): bump rocket-chip ... includes: - chore: add CSRs introduced by Smcsrind	2025-05-15 15:07:48 +02:00
linzhida	4b6f3e3000	fix(Smcsrind, Smstateen, Smaia): add missing permit check ... This commit makes the following changes: 1. Resets the CSRs introduced by the Smstateen extension, mstateen0, hstateen0, and sstateen0 to 0, and sets the CSRIND bit as writable. 2. Adds xireg2 to xireg6 introduced by the Smcsrind extension. 3. Implements the permission checks required when the Smaia, Smstateen, and Smcsrind extensions are all present.	2025-05-15 15:07:48 +02:00
Jiuyue Ma	f47ebf519e	fix(docker): Forward variables in the make command line to docker (#4686) ... Many variables in XiangShan Makefile can be overridden from command line. Without forwarding these to docker, commands executed in the container may produce unexpected results due to variable mismatches. Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>	2025-05-14 12:40:02 +02:00
lwd	7cf94e2c09	fix(StoreQueue): fix timeout of vecExceptionFlag when redirect (#4660) ... When the vector store that raised the exception is written back to the backend, the StoreQueue is too late to set the corresponding entries to `committed`, resulting in the `redirect` flush them, which results in the `vecExceptionFlag` being asserted due to the timeout not being cleared.	2025-05-14 14:31:30 +08:00