Commit 03938367 imports block_hptw_req to solve conflicts of syncing entries between sending mem req or sending hptw request. But block_hptw_req also made a bad timing path.
This patch use a different way to solve that. As mem req has higher priority, we could put hptw req before mem req.
pervious: cache.io.resp.bits.bypassed -> ptw.io.req.valid -> determine whether to use satp.mode or vsatp.mode by io.req.bits.req_info.s2xlate -> pmp.addr
now pmp.addr should always use satp rather than current_satp which do not rely on ptw.io.req.valid
during the `s_pm` state, we set `isMisalignReg` from `isMisalignWire`.
Therefore, when `state === s_pm`, `isMisalignReg` has not yet been set,
so we need to modify it to `isMisalignReg`.
There is a situation:
* Cycle 0:
* tlb_req_0
* Cycle 1:
* tlb_req_0 -> need_gpa_wire
* tlb_req_1
* ptw_resp
* Cycle 2:
* need_gpa_wire -> need_gpa
* tlb_req_1 & ptw_resp -> p_hit (Bypass)
In this situation, need_gpa is set and would not be cleared, while the
origin tlb_req is responsed by bypass, so the TLB freezed.
This patch tries to fix this issue, by adding a p_hit_fast to get
whether bypass hit in Cycle 1.
The software-check exception caused by Zicfilp has higher priority than
an illegal-instruction exception but lower priority than instruction
access-fault
### 1. Purpose of this Pull Request
XSPdb is a specialized Python pdb-based debugging tool for RISC-V IP
cores, customized for Xiangshan's difftest interface. It provides
GDB-like interactive debugging capabilities, integrating: Terminal
command-line interface, RTL-level waveform toggling, Automated script
replay, System snapshot save/restore, Register initialization
configuration
### 2. Changes Made
* **New Tool (`XSPdb`)**: The core Python scripts for XSPdb have been
added under `scripts/xspdb/`. This tool provides an interactive
debugging console with standard pdb commands (e.g., breakpoints, step,
continue, register inspection).
* **Build System Integration**: A new Makefile, `pdb.mk`, has been
created to define the build targets and logic required for XSPdb.
* **Makefile Modification**: The root Makefile has been updated to
include `pdb.mk`, integrating the new `pdb` target into the main build
system.
### 3. Usage
The new tool can be built and used via a new `make` target.
1. **Build the XSPdb package**:
```bash
make pdb NOOP_HOME=$(pwd)
```
2. **Run a simulation with the XSPdb**:
```bash
make pdb-run NOOP_HOME=$(pwd)
```
---------
Co-authored-by: Zhicheng Yao <yaozhicheng@ict.ac.cn>
When use `-xprop=xmerge` policy, the un-initialized `stage1Hit` in Mux()
will cause the X-state propagate to output port `io.resp.valid`. Fix it
by moving `idle` check out of Mux(), which means the `io.resp.valid`
only valid when `!idle`.
The generated RTL will changed from:
```
wire io_resp_valid_0 =
stage1Hit
? ~idle & hptw_resp_stage2
: ~idle & mem_addr_update & ~need_last_s2xlate
& (guestFault | w_mem_resp & find_pte | s_pmp_check & accessFault | onlyS2xlate);
```
to:
```
wire io_resp_valid_0 =
~idle
& (stage1Hit
? hptw_resp_stage2
: mem_addr_update & ~need_last_s2xlate
& (guestFault | w_mem_resp & find_pte | s_pmp_check & accessFault
| onlyS2xlate));
```
Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>
The nc (non-cacheable) attribute instructions go through the MMIO
channel. Unlike standard MMIO instructions, nc instructions can be
executed speculatively. For MMIO instructions, there's no need to check
whether the IBuffer is full when enqueuing. However, nc instructions
must check for IBuffer fullness.
This PR primarily fixes the issue where nc instructions were incorrectly
allowed to enqueue into the IBuffer even when it was full.
EMU Test / Changes Detection (push) Waiting to runDetails
EMU Test / Generate Verilog (push) Blocked by required conditionsDetails
EMU Test / EMU - Basics (push) Blocked by required conditionsDetails
EMU Test / EMU - CHI (push) Blocked by required conditionsDetails
EMU Test / Docker Build (push) Blocked by required conditionsDetails
EMU Test / EMU - Performance (push) Blocked by required conditionsDetails
EMU Test / EMU - MC (push) Blocked by required conditionsDetails
EMU Test / SIMV - Basics (push) Blocked by required conditionsDetails
EMU Test / Upload Artifacts (push) Blocked by required conditionsDetails
EMU Test / Check Submodules (push) Blocked by required conditionsDetails
EMU Test / Check Format (push) Blocked by required conditionsDetails
Release Jobs / build-xsdev-image (push) Waiting to runDetails
Some instances of this module may have io.out not connected. Under
normal circumstances, Chisel would not generate these modules, but due
to dontTouch here, these modules without io connections are still
generated. We do not yet understand the specific reason for this.
However, such Verilog cannot be synthesized on some FPGA platforms, so
in order to ensure the uniformity of RTL, we need to remove this code.
EMU Test / Changes Detection (push) Waiting to runDetails
EMU Test / Generate Verilog (push) Blocked by required conditionsDetails
EMU Test / EMU - Basics (push) Blocked by required conditionsDetails
EMU Test / EMU - CHI (push) Blocked by required conditionsDetails
EMU Test / Docker Build (push) Blocked by required conditionsDetails
EMU Test / EMU - Performance (push) Blocked by required conditionsDetails
EMU Test / EMU - MC (push) Blocked by required conditionsDetails
EMU Test / SIMV - Basics (push) Blocked by required conditionsDetails
EMU Test / Upload Artifacts (push) Blocked by required conditionsDetails
EMU Test / Check Submodules (push) Blocked by required conditionsDetails
EMU Test / Check Format (push) Blocked by required conditionsDetails
Release Jobs / build-xsdev-image (push) Waiting to runDetails
In the previous design, vaddr was sign-extended to PAddrBits to prevent
cases where the physical address width exceeds the virtual address
width. However, in the SV48x4 mode, the actual width of vaddr is 50
bits, which ended up being truncated to 48 bits.
In the onlyStage2 case, the generated guest physical address (gpaddr)
should match vaddr. But due to the truncation, gpaddr was also limited
to 48 bits, and the upper 2 bits were lost (set to zero).
To fix this bug, and to better support future extensions—vaddr is now
extended to the maximum physical address width (PAddrBitsMax) as defined
by the RISC-V specification.
EMU Test / Changes Detection (push) Has been cancelledDetails
Release Jobs / build-xsdev-image (push) Has been cancelledDetails
EMU Test / Generate Verilog (push) Has been cancelledDetails
EMU Test / EMU - Basics (push) Has been cancelledDetails
EMU Test / EMU - CHI (push) Has been cancelledDetails
EMU Test / Docker Build (push) Has been cancelledDetails
EMU Test / EMU - Performance (push) Has been cancelledDetails
EMU Test / EMU - MC (push) Has been cancelledDetails
EMU Test / SIMV - Basics (push) Has been cancelledDetails
EMU Test / Upload Artifacts (push) Has been cancelledDetails
EMU Test / Check Submodules (push) Has been cancelledDetails
EMU Test / Check Format (push) Has been cancelledDetails
Nightly Regression / Nightly Regression(master) - Checkpoints (push) Has been cancelledDetails
Nightly Regression / Nightly Regression(kunminghu-v3) - Checkpoints (push) Has been cancelledDetails
`MemBackTypeMM`: requesting region backed by main memory (`!pmp.mmio`)
(don't care pbmt)
`MemPageTypeNC`: requesting `pbmt=nc` region (don't care backtype)
We need to tell L2 Cache about this via Tilelink to make it work.
This PR:
- ICache: Always work on main memory (`!pmp.mmio && pbmt=pmp`)
- `MemBackTypeMM` is always true
- `MemPageTypeNC` is always false (keep default value)
- Ifu/InstrUncache: Might be working on main memory, but pbmt=nc/io. Or
on real mmio region
- `MemBackTypeMM = !f3_pmp_mmio`
- `MemPageTypeNC = f3_itlb_pbmt === Pbmt.nc`
---------
Co-authored-by: Yanqin Li <maxpicca@qq.com>
* add bitmap wakeup the page table cache check hit state;
* modify the calculation of Bitmap permission data address, all of which
are accurate to 4K pages, and only return ITLB/DTLB page tables with 4K
granularity when permission check is enabled.
* fixed the issue that two requests in Bitmap check were merged and
missed the update permission;
* modify the permission query results of Super Page that are no longer
cached in PageTableCache;
* fixed the issue of l0Pets splicing format of PageTableCache output;
* fixed the issue that bitmap_checkfailed registers in PTW and HPTW were
not reset;
* fixed the issue that bitmapCacheEntry was not initialized;
* fixed the issue of Napot entry jmp_bitmap_check process;
* In BitmapCheck use parameters to selsct cf bits;
EMU Test / Changes Detection (push) Waiting to runDetails
EMU Test / Generate Verilog (push) Blocked by required conditionsDetails
EMU Test / EMU - Basics (push) Blocked by required conditionsDetails
EMU Test / EMU - CHI (push) Blocked by required conditionsDetails
EMU Test / Docker Build (push) Blocked by required conditionsDetails
EMU Test / EMU - Performance (push) Blocked by required conditionsDetails
EMU Test / EMU - MC (push) Blocked by required conditionsDetails
EMU Test / SIMV - Basics (push) Blocked by required conditionsDetails
EMU Test / Upload Artifacts (push) Blocked by required conditionsDetails
EMU Test / Check Submodules (push) Blocked by required conditionsDetails
EMU Test / Check Format (push) Blocked by required conditionsDetails
Release Jobs / build-xsdev-image (push) Waiting to runDetails
This should not happen on a normal MMIO req (mmio is sent only when last
instruction is commited, so no redirect will happen).
But on a pbmt=nc area, we can do speculative fetch: #3944, so it can be
cancelled by backend/ifu redirects, we should reset MMIO fsm and cancel
(or flush) requests from InstrUncache.
The Napot extension requires that the lower 4 bits of the page table's
PPN satisfy 4'b1000. However, `pte_in.getPPN()` contains the original
PPN value, while ptw_resp.ppn has already been truncated once. So we
should use `pte_in.getPPN()` here to check Napot pages.
lihuijin
good-circle
Xu, Zefan
tianxin
Tang Haojin
Xin Tian
Yinan Xu
lwd
Yanqin Li
Zhaoyang You
Guanghui Cheng
xu_zh
Muzi
SFangYy
Jiuyue Ma
Anzo
Ziyue Zhang
zhou tao
cz4e